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CET1172C Lecture #12 - ATA Specifications and HDD Sector Addressing

Materials:
Working complete PC
Blank Diskette
Student Diskette, "New Boot A Ver 2.0+"
Student CD-ROM, "Room 6359"
Objectives:
The student will become familiar with the ATA specifications including,
The evolution and development of ATA,
The capabilities of each controller generation,
The capabilities of each ATA generation's IDE HDD's,
The introduction of Serial ATA,
The student will become familiar with how the system accesses sectors on the HDD,
The student will learn about early BIOS limitations,
and the various common BIOS translations,
and the modern BIOS sector addressing methods.
Competency:
The student will understand the nature and function of the modern ATA and EIDE parallel hard drive and controller as well as the Serial ATA hard drive and controller and be able to identify, install, troubleshoot, and upgrade system's hard disk storage subsystems. The student will understand the original low level BIOS hard drive sector addressing scheme and the various modifications to the original geometric coordinate system called translations. The student will learn about 28-bit and 48-bit LBA methods that have been added to the modern BIOS to allow low level access to much larger hard drives.
The ATA Controllers
  1. The ATA controllers are at the other end of the standard 40-pin IDE or 80-wire/40-pin UDMA data cables from the hard drives. There has been a steady evolution in the power, speed, and capabilities of the ATA controllers that has kept pace with the incredible pace of advancement in the hard drives capacity in particular.

  2. Below is a listing of the ATA controllers, their features, capabilities, modes, and maximum data transfer rates:

    ControllerPIO ModesUDMA ModesTransfer Rate   Features Introduced
    ATA-10-2 - 8.33MB/secFirst IDE controller, defined cables, signalling, master/slave IDs, and the first IDE language. No formal support for translations resulted in the 504MB HDD size limit.
    ATA-20-4 - 16.67MB/secTranslations formally defined, introduced support for PCMCIA, APM, improved (E)IDE language. Formally defined the secondary EIDE controller.
    ATA-30-4 - 16.67MB/secIntroduced SMART, improved signaling including autotermination, ECHS mandatory support HDD up to 8.4GB, declared 8-bit DMA modes obsolete
    ATA-40-40-233.33MB/secIntroduced UDMA and optional 80-wire cable, introduced 28-bit LBA, integrated ATAPI support.
    ATA-50-40-466.67MB/sec80-wire UDMA cable autodetection mandatory, UDMA modes 3 and up require the cable. Introduced DTR up to 66MB/sec.
    ATA-60-40-5100MB/secIntroduced UDMA mode 5, introduced 48-bit LBA
    ATA-70-40-6133MB/secIntroduced UDMA mode 6, end of parallel ATA

  3. The major improvements in this series are between the ATA-1 controller and the ATA-2 controllers in which the IDE language was vastly expanded and the secondary controller was officially defined. Western Digital marketed the improved controller and its drives as "EIDE" (Enhanced Integrated Drive Electronics) and the term is now an industry standard acronym refering to hard drives as well as ATA controllers from ATA-2 to ATA-7. The ATA-2 controller was wrapped into the PCMCIA - Personal Computer Memory Card Industry Association specification and also wrapped that specification into itself. This ensures 100% compatibility and reliability for controllers and hard drives interfacing with this laptop expansion bus. This 16-bit/16.66MHz bus was later renamed the PC Card bus. The modern 32-bit/33MHz version incidentally is called Cardbus.

  4. Another huge improvement occurred in the step from the ATA-2 controller to the ATA-3 controller in which the devices are expected to have superior capabilities of autoterminating on the IDE bus and the signal timing, waveforms, and integrity at the electronics level was vastly improved as well. The ATA-3 controller was also capable of handling each device individually at its maximum performance rather than locking the controller to the speed of the slowest device. The legend of keeping optical drives on the second controller and not attached to the same controller as the hard drive was no longer necessary because of this improvement (although it still makes some sense since a large data transfer from the optical drive will still bog down the entire channel regardless).

  5. Another innovation introduced with the ATA-3 controller is S.M.A.R.T. - Self Monitoring Analysis and Reporting Technology usually written with the periods. The hard drives starting with the third generation EIDE (accompanying the ATA-3 controller) have built in sensors that can detect if the spindle motor is not maintaining a steady RPM, or if the drive has to use ECC data in the intersector gaps to reconstruct the contents of the sector. None of these things would be noticeable to the outside world, that is the hard drive would appear to still be functioning normally, but these things could mean that the hard drive about to fail. S.M.A.R.T. drives will report the problem. However, the PC market was very slow in implementing the ability to receive the message from the hard drive. Most system can only receive the "flag" that the hard drive detects internal trouble during the POST, and the BIOS will then display a generic warning that the hard drive may fail soon. Modern hard drive utility programs included with the hard drive can also run the S.M.A.R.T. diagnostic, but there appear to be very few programs that can actively monitor the drive while the operating system is up and running and in use.

  6. The step between ATA-3 and ATA-4 controllers was probably the largest functional improvement that the end user would notice by integrating ATAPI support which would later include the "El Torito" specification which defined the BIOS boot strap loader function and the files and their contents for making bootable CD-ROM's (as well as any other technology using ATAPI including Iomega ZipTM Drives). This carries over into this controller so that it is capable of looking for these files and launching an OS if they are present and in the correct format. This controller also introduced the UDMA controller which functions similarly to the old AT DMA chip but with vastly superior performance since it is operating on the PCI bus.

  7. The ATA-5 controller brought far faster UDMA modes as well as autodetection of the 80-wire UDMA cable. If the controller does not detect the cable it will force the channel to run at UDMA mode 2 even though the drive and controller can run faster. This is because the high frequency of higher UDMA modes will cause large numbers of data transfer errors across the wire. UDMA does pack a CRC with the block of data being transfered from the drive to the controller and vice versa so the devices will detect the error incurred across the cable and retry the transfer, but this will occur so often that the effective transfer rate at higher modes on the old cables will be slower than just defaulting to UDMA mode 2 where almost no data loss and retries would occur.

  8. The ATA-6 controller brought 100MB/sec transfer rates and formally defined 48-bit LBA. ATA-6 controllers claim that non-LBA mode transfers from controller to drive have been rendered "obsolete". If the drive does not understand true 28-bit or 48-bit LBA then the transfers cannot occur. I have observed "Normal" (what many BIOS manufacturers call CHS) as an available option and used it on the ATA-6 controllers in the lab so this appears to be either discretionary on the manufacturer or perhaps they really mean deprecated or the BIOS is using LBA to communicate CHS requests from the OS to the HDD. ATA-6 controllers introduce a small modification to the IDE language that allows an IDE command request from the controller to the drive for a 16-bit number to hold the number of sectors being requested in a read/write operation. The old language used an 8-bit number for this field which meant that a controller could request to read up to 255 sectors with a single command. Using the 16-bit value allows the controller to ask for up to 65,535 consecutive sectors from the drive with a single IDE command. As files swell in size this does make more sense.

  9. The latest ATA-7 controllers boast 133MB/sec UDMA Mode 6 transfer rates. These are the last of the parallel ATA controllers because SATA is already being used and the committees are working on these specifications now. SATA-I originated as the ATA-8/SATA-I specification indicating full backwards compatibility. While there are many low level changes, the SATA-I controller is in theory capable of communicating with older devices, but if it is not given a 40-pin connector, then there would be no way to attach such devices to it. SATA-I is also erroneously refered to as "SATA-150" but this is the Serial ATA data transfer mode, using UDMA, of 150MB/sec. Since this is greater than the DTR of the classic PCI bus (32-bit/transfer at 33MHz = 133MB/sec) SATA-I controllers must be interfaced to the system on a superior expansion bus. When included on the motherboard as an integrated peripheral, they are interfaced with a 64-bit wide standard PCI bus attachment, even though no such expansion slots are included on the motherboard. This bus attachment has a maximum DTR or 266MB/sec and will suffice.

  10. With the release of SATA-II, erroneously called in many cases "SATA-300" which refers to the Serial ATA data transfer mode of 300MB/sec even the "normal" PCI bus controller driving a 64-bit wide bus is not fast enough to support the controller. Most motherboard chipsets that include the SATA-II controller feature PCI-Express. Since the peripheral can be attached to this bus with as many "lanes" as it needs, this is the only common end-user general purpose expansion bus that has the bandwidth to support the controller. It appears that fewer of these controllers are offering parallel connectors, they are already becoming a deprecated technology and eventually the parallel transfer ATA controllers and their associated devices will be obsolete.

Hard Drive Geometry
  1. There have been several different schemes used for addressing the storage locations or sectors of an HDD. Originally the motherboard BIOS designers allowed the geometry of the HDD to be stored in the CMOS RAM with the following values:

    ParameterStored asAllowed Values
    Cylinders10 bit number 2100-1023, total=1024
    Heads8 bit number 280-255, total=256
    Sectors/track6 bit number 261-63, total=63
  2. Remember that there is no sector=0 in hard drive geometry. This totals 24 bits or three bytes set aside for this information. However, the ATA controller developed years later for communicating with IDE hard drives stores the geometry of the HDD differently. This was done to allow low level access to the hard drives that had become much larger than they were in the beginning. The ATA controller queries the drive during the POST and stores the geometric values of the drives inside its own CMOS like this:

    ParameterStored asAllowed Values
    Cylinders16 bit number 2160-65,535, total=65,536
    Heads4 bit number 240-15, total=16
    Sectors/track8 bit number 281-255, total=255
  3. Because of these design differences it was not possible for the BIOS code to send a number of cylinders, larger than what it was designed to store, to the ATA controller so the extra cylinder capacity of the ATA controller went unused. Likewise, the ATA controller could not handle a request for a head numbered higher than 15 without an error. Because of these discrepancies, when the first ATA controller was installed onto the motherboard, the BIOS driver code was designed to avoid generating any number that it could not handle or that the ATA controller could not handle.

  4. The largest cylinder number that both BIOS and the ATA controller can pass back and forth then is 1023. Since these start with cylinder 0 then the largest number of them that is supported on a hard drive is 1024. Similarly the largest head number is 15 (total = 16) and the largest sector number is 63. Since sectors are numbered starting with sector #1 then the largest total number of sectors/track that the system could handle was 63. This yields a total maximum capacity for the hard drive of 1,032,192 sectors (1024 x 16 x 63). Multiply this by 512 bytes/sector = 528,482,304 bytes. This is the classic CHS limit (no translations) which is 528 million bytes or 504MB. HDD's quickly swelled to this capacity...something had to be done.

  5. It was found that if the BIOS code and the ATA controller were set up for it they could "lie" to each other. They could send modified values back and forth taking advantage of the BIOSes full 24 bit number for holding the geometry capacity. This process is called translations. Phoenix BIOS was one of the first to develop a geometric translation method called ECHS or Enhanced CHS (Cylinders/Heads/Sectors.) The Phoenix BIOS translation method uses a very fast bitshifting algorithm to multiply and divide the translated numbers by powers of two which is why it is also refered to as "phoenix bit-shifting translations." As it turns out, there were no fixed standards for the implementation of the Phoenix BIOS "ECHS" and many BIOS makers developed their own methods of translating the large hard drive's geometry into numbers that the BIOS could handle.

  6. Here is a table of the various limitations and what causes them:

    Maximum HDD CapacityTranslation Method
    504MB(528million)No translations: BIOS Cyl=1024 x ATA Heads=16 x BIOS sec/track=63 x 512bytes/sec
    2GB(2.1billion)No translations: BIOS uses 12bit Cylinder number in CMOS, 4096x16x63x512
    3.2GB(3277MB)Early Phoenix EDD BIOS versions 4.x had a bug that caused a boot crash with HDD's > 3.2GB
    4GB(4.2billion)"Corrected" ECHS, divides Cyl by 2 until it falls at or below 1024 and doubles the number of heads each time. DOS/Windows crash if BIOS reports 256 heads (0-255) so this stops at 1024x128x63x512
    7.5GB(7.9billion)A "Revised" Phoenix ECHS that can implement a fake geometry based on 240 heads: 1024x240x63x512
    7.8GB(8.4billion)"LBA Assisted" works out a geometry up to BIOS limit but holds the number of heads to 255: 1024x255x63x512
    32.25GB(33.8billion)BIOS divides the capacity the drive reports by (16x63x512). If this results in Cyl > 65535 the BIOS hangs on boot up because it cannot deal with the number.
    130.5GB(136.9billion)True 28-bit LBA uses ATA controller limits: 65536x16x255x512
    128PB(a.k.a. 144PB)The current ATA-6+ controllers use 48 bit LBA: 248=281,474,976,710,656 x 512bytes/sector
    9.44ZBAll modern motherboards implement EDD BIOS Version 3.0+ which is 64 bit LBA. 264=18,446,744,073,709,551,616 x 512bytes/sector
  7. When an HDD has too many cylinders for the BIOS to store the number it will divide the number of cylinders by two until it falls below 1024. So if the HDD's geometry is actually Cyl=7000, Hds=16, Sec=63, then 7000/2 = 3500 which is still too large: 3500/2 = 1750...1750/2 = 875 which is an acceptable number to BIOS. Now it will multiply the number of heads by the factor that was divided into the cylinders, so 16 x 8 = 128. The BIOS will store the geometry as Cyl=875, Hds=128 and Sec=63. All fit into the CMOS values. The ATA controller will be warned of the move and the BIOS is coded to send the values to the ATA controller so that it will not cause errors.

  8. The full capacity of the BIOS values is allowed when ECHS is fully implemented to allow flexibility in dividing integers into the cylinder count. In that case the full BIOS limit numbers can be employed: Cyl=1024 x Hds=256 x Sec=63 = 16,515,072 sectors can be requested. Times 512 bytes/sector = 8,455,716,864 bytes. This is the full Phoenix bit shifting ECHS limit with a capacity of 8.4 billion bytes or 7.8GB. The problem is that IO.SYS has a design flaw that causes it to hang if the drive reports 256 heads. Since IO.SYS was at the bottom of almost all operating systems on these hard drives, this translation scheme had to be "Corrected" quickly to prevent the crash at boot up. The "Corrected" Phoenix bit-shifting translation simply stops the division of the Cylinder number and consequent multiplication of the head number when the head number reaches 128. The next doubling would be 256 which would cause IO.SYS to crash. This effectively lops off the maximum capacity of the translation method at C=1024 x H=128 x S=63 x 512 = 4,227,858,432 bytes or approximately 4.2GB (as hard drive manufacturers define a GB equal to exactly 1 billion bytes) or 3.94GB (in true binary GB as reported by FDISK). ECHS would be "Revised" since this was a harsh "quick fix" to the crashing IO.SYS problem.

  9. In the "Revised" Phoenix bit-shifting translation the standardized number of heads that an EIDE drive reports to BIOS is 16 and the standardized number of sectors/track that the drive reports is 63. "Revised" ECHS will assign the number of heads to 15 and because the change makes the new number of heads 15/16ths of the original actual number of heads, the number of cylinders must be adjusted up by the same factor so the number of cylinders is multiplied by 16/15ths or 1.0666. To illustrate:

      Drive reports: Cyl = 10,000 Heads = 16 Sectors = 63
      Revised ECHS BIOS assigns: Heads = 15 (16 x 15/16) so,
      Revised ECHS BIOS assigns: Cyls = 10,000 x 16/15 = 10,666
      Notice that: 10,000 x 16 x 63 = 10,080,000 sectors and
                   10,666 x 15 x 63 = 10,079,370 sectors which is very close
      Now apply the ECHS formula:
       Cyls = 10666 ÷ 2 = 5333 therefore Heads = 15 x 2 = 30
               5333 ÷ 2 = 2666 therefore         30 x 2 = 60
               2666 ÷ 2 = 1333 therefore         60 x 2 = 120
               1333 ÷ 2 =  666 therefore        120 x 2 = 240
    
  10. At this point the number of cylinders is below 1024 so BIOS can use the value and the number of heads is below 256 so IO.SYS will not crash either. Far more capacity is supported with this pre-translation adjustment such that the largest drive supported would be: C=1024 x H=240 x S=63 x 512 = 7,927,234,560 bytes or 7.9GB (as the hard drive manufacturers define a GB) or 7.38GB (in true binary GB as FDISK reports).

  11. Another form of ECHS was also developed by the BIOS manufacturers and became popular around this time as well called "LBA Assisted ECHS" or "Assisted LBA" or some just called it "LBA" but this is very misleading. True LBA will be covered below. In LBA Assisted ECHS translations the Phoenix bit-shifting scheme is completely abandoned. When the BIOS autodetects an EIDE drive it uses the standard IDE language "Drive Identify" command (to the I/O address in the 1F0h range by the way) The drive responds with a series of status I/O address bytes holding a lot of information including the CHS geometry numbers and its LBA capacity.

  12. Let's say the drive reports: C=16,288 , H=16 , S=63 and the LBA capacity = 16,418,430 total sectors (just the total number of sectors on the drive). LBA Assisted ECHS will assign the total number of heads = 255 and the total number of sectors/track = 63 because the capacity is larger than 8,257,536 sectors which is the "safe" limit for using true Phoenix bit-shifting ECHS (C=1024, H=128, S=63). Now it will divide the LBA capacity by these assigned values to arrive at the total cylinders to use with the BIOS: 16,418,430 ÷ (255x63) = 1022. Now for the BIOS the geometry will be C=1022, H=255, S=63. This BIOS will use a formula to translate geometry requests to read the drive converting them into pure LBA values and then ask the drive for LBA sector #x. The drive wil never be asked for the sector at C=x, H=y, S=z, hence the terminology here: LBA Assisted ECHS. This translation method requires far more calculations per read/write request than the very fast Phoenix bit-shifting translation method and using 32-bit hard drive drivers which run in high speed RAM versus very low speed EEPROM chips would greatly improve the performance on these machines when running Windows. Either way this form of ECHS allows the maximum drive to have a geometry of: C=1024 x H=255 x S=63 x 512 = 8,422,686,720 bytes or 8.4GB as hard drive manufacturers define a GB) or 7.84GB (in true binary GB as FDISK reports).

Logical Block Addressing

  1. Hard drives quickly surpassed this solution as well... When a hard drive exceeds 8.4 billion bytes then ECHS will not work. Logical Block Addressing was implemented in which the full 28-bit value stored by the ATA controller would be used to request sectors from the HDD. The LBA value is a pure sector number. Internally the HDD itself can refer to a sector as "the sector located at C=0, H=0, S=1" which is the geometry coordinate of the sector. It can also refer to this sector as "the sector #0" which would be the LBA coordinate for the same sector (the first physical sector of the drive). In that case "the sector at C=0, H=0, S=2" (geometric coordinate) would be "the sector #1" (LBA coordinate) and "the sector at C=0, H=0, S=3" (geometric coordinate) would be "the sector #2" (LBA coordinate) and so on. Since the ATA controller uses a 28-bit number to store CHS numbers the system can use LBA numbers up to 28-bits to access sectors on the drive since that fits in the ATA controller's allowed CHS parameters numbers. This allows larger geometries to be addressed.

  2. The motherboard BIOS has to be rewritten for this to work. New values are stored in CMOS for the HDD's geometry to accommodate the 28-bit values that are required also. In this new CMOS location the new 28-bit LBA values for up to four HDD's can be stored. The motherboard BIOS 16-bit ATA controller device driver interface must also be completely rewritten. This was done to accommodate the ECHS translations also. The LBA additions to the interface which programs access through software Interrupt number 13h are called the Int 13h extensions collectively for ECHS and LBA. The Extended Int 13h handler of the BIOS ATA controller driver will request the sectors in order from the hard drive without referring to the geometry at all. The hard drive onboard IDE controller will internally translate the LBA number into where it is actually located on the platters and tracks. The ATA controller can store Cyl=65,536 (16-bit value)x Hds=16 (4-bit value) x Sec=255 (8-bit value) = 267,386,880 sectors. Remember using CHS there is still no sector=0. And the total number of bits used there is 16 + 4 + 8 = 28-bit. Multiply this number of sectors by 512 bytes/sector = 136,902,082,560 bytes. This is the recently overrun 136.9GB 28-bit true LBA BIOS hard drive capacity limit. Notice that the 28-bit format is not true LBA but is in fact CHS geometry but using the ATA controller's capabilities instead of the BIOS'es limited CHS capabilities.

  3. A few years back Phoenix BIOS saw the problem escalating and invented a BIOS that could store a 64-bit LBA value: 264=18,446,744,073,709,551,616 sectors. Multiplied by 512 bytes/sector = 9,444,732,965,739,290,427,392 bytes or 9.44ZB (Zettabytes). Even at Moore's law's current rate of computer age technological advance, HDD's will not reach this capacity until the year 2055. This is now known as EDD Version 3.0 (and above) or Enhanced Disk Drive BIOS and is now standard. Meanwhile the ATA controllers had to evolve for the first time ever (it was always the motherboard BIOS'es shortcomings that were the problem) because they are the ones stuck with the 28-bit numbers for holding the HDD geometry. So the new ATA-6 controller (the one that introduced UDMA-100) introduced a new internal design that would communicate with the HDD using 48-bit LBA: 248=281,474,976,710,656 sectors times 512 bytes/sector = 144,115,188,075,855,872 bytes or 144PB. But this is the erroneous even quintillions, just like the erroneous even billions of the 8.4"GB" limit. The 48-bit LBA is exactly 128PB(inary), but like the others, you will likely encounter it described as the "144PB" limit.

Review Questions
  1. List and describe the seven generations of ATA controller:




















  2. What ATA controller introduced the possibility of begin able to boot from a CD-ROM? What is the additional specification, mainly for the BIOS that actually allows the system to boot from the CD-ROM?


  3. What ATA controller introduced SMART? Describe the technology.








  4. The term "EIDE" was used as a marketing name by what company? What technology were they refering to? What does the term now refer to?


  5. What was the first ATA controller to feature a standardized secondary channel? What was the maximum number of hard drives that could be attached to such a controller? How many per channel?


  6. What was the first ATA controller to feature a high speed integrated direct memory access controller chip? What is this technology called? What was its maximum DTR (on the first controller to use it)?


  7. What was the first ATA controller to support LBA? Which version of LBA did it use (bits used to address sectors)?


  8. What was the first ATA controller to support the standard laptop expansion bus? What is the modern name of this bus?


  9. The fastest parallel ATA controller has what maximum DTR? This is also the maximum DTR of what general purpose expansion bus?


  10. What is the maximum DTR of SATA-I? How can a "standard" PCI bus controller support SATA-I?


  11. What is the maximum DTR of SATA-II? What is the most common general purpose expansion bus that can support it?


  12. Based on the information provided above list the maximum DTR for UDMA Modes 2, 4, 5, and 6. Look up the maximum DTR for UDMA Modes 0, 1, and 3.


  13. Very rarely does any technology in the PC industry suddenly declare a technology obsolete. What ATA specification made such a declaration? What was rendered obsolete?


  14. What ATA controller introduced support for the UDMA cable? What is the difference between this cable and a standard IDE cable? What controller introduced autodetection of this cable? If absent what is the maximum UDMA mode that the controller will allow? Why?








  15. What ATA controller introduced the ability to fully recognize hard drives larger than 136.9GB? What sector addressing scheme makes this possible?


  16. What was the first ATA controller that could fully recognize hard drives larger than 8.4GB? What technology within the PC imposed this hard drive capacity limit for years?


  17. Some fairly modern (Pentium II/III based PC's) suffer from the "divide by 16 x 63" BIOS bug. Even though they are using 28-bit LBA such a BIOS may hang after attaching a hard drive larger than how many GB (give the hard drive manufacturer's "even billions" GB value)?


  18. You attach a known good "200GB" "ATA133" hard drive and cable to an unknown system that then reports on the BIOS summary screen that the hard drive is using UDMA Mode 4, what ATA controller does this PC have? What size will it most likely report for the hard drive? Why?


  19. You attach a known good "200GB" "ATA133" hard drive and cable to an unknown system that then reports on the BIOS summary screen that the hard drive is using PIO Mode 4, what is the latest ATA controller this PC can have? What size will it most likely report for the hard drive? Why?


  20. You attach a known good "200GB" "ATA133" hard drive and cable to an unknown system that then reports on the BIOS summary screen that the hard drive is using PIO Mode 2, what is the latest ATA controller this PC can have? What size will it most likely report for the hard drive? Why?


  21. You attach a known good "200GB" "ATA133" hard drive and cable to an unknown system. Low level hard drive programs then report that the hard drive has 240 heads. What translations are being used? What is the maximum capacity that the BIOS will recognize? What is the latest ATA controller that this drive is attached to?


  22. You attach a known good "200GB" "ATA133" hard drive and cable to an unknown system. Low level hard drive programs then report that the hard drive has 255 heads. What translations are being used? What is the maximum capacity that the BIOS will recognize? What is the latest ATA controller that this drive is attached to?


  23. You attach a known good "200GB" "ATA133" hard drive and cable to an unknown system. Low level hard drive programs then report that the hard drive has a capacity of 186.3GB. What translations are being used? What is the oldest ATA controller that this drive is attached to? What is the lowest DTR it should be capable of?


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