CET1172C Key Terms Study Guide

The student should Copy and Paste the information below into a Notepad or Word document and print it. Most of the terms below are not actually acronyms, but some are contractions, you should know what words were contracted to create the terms. The student should then read a few definitions of each term and write out a definition on the back of a 3x5 card with the term on the front of the card. Then practice by shuffling your cards, then spell each one out and then define it. Then flip to the next card. When the student can go through the deck without difficulty a large part of the final exam is in the bag!

2D and 3D acceleration	2 Dimension accelerator is a video card with a GPU designed to build a single image on screen at a time. A 3 Dimension accelerator is a video card with a GPU that is powerful enough to construct several layers of bitmaps simultaneously for rendering as a single image on screen or to be presented one at a time in a series to create full speed full screen animation. A video card without 3D acceleration will most likely fail to display any form of computer video file.
"A" connector	Standard USB connector for the USB host controller. The host itself has a female "A" connector and the cable has a male "A" connector.
aperture grille	The divisions on the inside surface of the CRT - Cathode Ray Tube, that separate the extremely small (beyond normal human sight resolution) Red, Green, and Blue spots that the eyes interpret blended thus creating any possible color.
aspect ratio	The ratio of the screen width to screen height. For example, a television with a CRT has an actual measured width of 18 inches, and an actual measured height of 13.5 inches. The aspect ratio of this CRT is 18 to 13.5, dividing both of these numbers by 4.5 yields 4 to 3 which is then written "4:3" Large flat panel LCD's invented during the PC era for the PC's do not have to follow the old television image transmission standard aspect ratio and so newer wide screen aspect ratios such as 16:9 and 2.5:1 have emerged.
"B" connector	When attaching an external USB peripheral, the "B" connector is used on the peripheral itself, while the "A" type connector is used on the host controller, either integrated into the motherboard or on an expansion card within the system unit. This means that the USB external device cable has a male "A" at one end and a male "B" at the other end. This prevents the user from inadvertantly attempting to connect one host controller on one PC to another, which would cause a power short circuit aside from the fact that any USB subsystem can only have one controller on it.
BIOS boot sequence	A setting found within the BIOS Setup Utility that allows the user to change the order of the devices that the BIOS Boot Strap Loader will attempt to boot from. Modern sixth generation BIOS boot sequence is fully configurable to allow any order of the recognized devices both fixed and removable media types. It is useful to have the optical drive first if the hard drive is malfunctioning in order to bypass a corrupted MBR.
BIOS boot strap loader error	A message displayed by the BIOS Boot Strap Loader code indicating that no suitable boot sector was found on any device in the BIOS Boot Sequence list of devices. Wording of this message varies between BIOS manufacturers and can be caused by: 1) Device has been removed from the BIOS Boot Sequence - simply check the setting. 2) Device is not recognized by BIOS - enter Setup and attempt to detect it again. 3) Device does not have a suitable boot sector - boot to alternate disk and check with FDISK: needs to have defined partition(s) and one set active (HDD's) 4) Device is attached incorrectly - check the jumper settings and cable attachments. 5) Device is malfunctioning - replace with a known good component and try again.
host controller	Any peripheral that attaches to a standard expansion interface on the PC and that makes itself available as an attachment point for other peripherals. The USB host controller attaches directly to the PCI bus and provides the attachment point for internal and external USB peripherals. The SCSI host controller attaches to the PCI bus and either internal or external SCSI devices can then be attached to it.
balanced signaling	method of exchanging electrical physical signals between two independent devices in which each of two physical wires carries an equal and opposite polarity voltage representing the information. The receiver only needs to detect the difference in polarity on the two wires in order to detect the data. This makes balacned signaling also called "voltage differential" signaling very robust. Balanced signaling is the standard transmission method used by USB as well as modern SCSI interfaces.
cache	Any technology in which a slower form of memory is prefetched into a faster form of memory. Hard drives data can be cached into regular RAM which is roughly 1000 or more times faster. The management of this "disk cache" need only anticipate what information might be requested from the drive next, and read it up into RAM so that when it is requested it can be forwarded from the disk cache in RAM instead of having to read it up off of the slow actual platters of the drive. DOS has a disk cache utility called SMARTDRV.EXE that does this with up to an 85% "hit ratio" which means that 85% of the requests that the user makes have already been read from the drive into the RAM cache area. Windows incorporates its own 32-bit version called the VCACHE and begins prefetching an executable as soon as the mouse hovers over its icon, greatly improving the speed of the launch of the application.
chip creep	Dual Inline Pin packaged chips mounted into DIP sockets that undergo rapid, repeated and continuous heating and cooling will slowly but steadily work the pins up out of the socket until they are loose enough to loose contact with the socket and fail. They must then be manually pressed back down securely into the socket again in order to work. Early PC RAM came packaged in DIP chips and suffered badly from chip creep inspiring the invention of the modern RAM modules that clamp into place.
chipset	The collection of circuitry chips mounted directly onto the motherboard that are designed specifically to interface directly with the microprocesor itself. These chips can translate the signals coming from the CPU as well as signals coming from the peripherals and going to the CPU by changing their speeds, currents and even encoding when necessary to match the signal format of the CPU for information heading toward it, or to match the signal format needed by the peripheral for signals heading out from the CPU.
Celeron	The marketing name for the economy versions of the Intel Pentium II and beyond generations of microprocessor. The original Celerons were by definition regular Pentium II's with less built in cache, but the definition has now widened to include not only variants of the regular product with less internal cache but also with slower internal cache, less support for external cache, lower front side bus speeds, as well as lower internal core clock multipliers. All of these tend to make Celerons slower and therefore cheaper than the regular versions of the microprocessor.
Centrino	An Intel marketing brand name tied to their very fast and enormously successful Pentium M processor. Because "Centrino" became more recognizable and popular than the Pentium M itself, this marketing strategy paid off: end-users did not want Pentium M processors (which is exactly why a Centrino based system was so fast, instead they wanted Centrino based systems. Since the Centrino based system included a particular Intel motherboard chipset and a particular family of Intel wireless network interface card, Centrino successfully forced laptop manufacturers to pay for these additional products from Intel so that they could label their laptops "Intel Centrino Inside."
clock multiplier	Process started with the 80486DX processors in which the internal core of the CPU itself runs as a multiple of the speed of the front side bus. This allows the processor to complete the decoding and execution phases of the machine language execution cycle faster. Also because these processors and all later generations have an internal L1 cache, the processor can often complete the machine language fetch at the multiplied speeds as well giving the illusion that the CPU does in fact run at some speed between the internal multiplied clock speed and the external front side bus speed. The actual performance of such a processor will depend entirely on the efficiency of the MMU - Memory Management Unit; the section of the CPU that manages internal and external caches. The larger these caches and the more intelligent the MMU the more the CPU will appear to run at or near the multiplied core speed. With smaller caches and less efficient MMU's the CPU will appear to run closer to the FSB speed. The 486 generation had a single 8KB L1 running at core speed, a maximum support for up to 256KB of L2 running at FSB speed and a 2nd generation MMU. With this modest architecture a 486DX4/100 (core multiplied to run at 3 times the 33MHz FSB) would enjoy about an 85% cache MMU "hit ratio" or appear to run at about 85MHz. The latest processors have very large (1MB or more) internal L2's and very sophisticated MMU's and appear to run at or above 90% of the clock multiplied core speed.
coaxial	A form of cable in which the two wires that connect the two peripherals are housed within a single sheath with the signal carrying wire running through the center surrounded by insulation which is then surrounded by the second ground wire in the form of a meshlike cylinder around the central wire. Coaxial is therefore a method of cabling used in unbalanced signaling systems. by surrounding the central signal carrying wire by a cylindrical ground connectivity wire this serves not only to pass the common ground for the signaling between the two devices it also serves to shield the signal carrying wire from external interference.
codec	Abbreviation of the term coder/decoder. Codecs are dedicated software virtual device drivers that encode raw data streams into a specific format and can also decode encoded data streams back into the raw format again. Codecs are often used for data compression. A typical pixel by pixel stream of information required to display a full screen could require over a megabyte, but can by using JPEG - Joint Photographic Experts Group, a common standard form of still video data compression be reduced to a small fraction of this size. If a system has the JPEG codec then when the file in JPEG format is opened, the format is recognized and the contents are forwarded to the JPEG codec which decompresses the information and then forwards the raw image stream to the requesting application (web browser, photo editor, etc.)
color depth	During the development of superior video controller technologies it was recognized that increasing the number of colors that could be rendered by the video RAMDAC chip could greatly improve image quality. VGA in standard maximum resolution supports 16 possible colors on screen at one time which means each pixel's information is being represented in the video RAM by 4 bits (numbers 0 to 15 for the sixteen colors). 8-bit color depth means that each pixel is being represented by 8-bits or one byte. Since a byte can store 0 to 255 for a total of 256 different numbers, 8-bit color depth means that the video RAMDAC can display up to 256 different colors on screen at one time. 16-bit can represent up to 65,536 different colors at a time and is called "High color" Images begin to look photographic in quality in high color. 24-bit color depth is called "true color" and the images are extremely high quality approaching photographic or television in quality. Motion video pretty much requires true color to be tolerable. 32-bit true color adds another 8-bits for altering saturation/brightness/contrast which greatly improves the quality of oranges/yellows and browns which are the most difficult to display in Red-Green-Blue based display technologies (All modern display technologies are RGB based.)
color palette	The full set of defined colors that the video RAMDAC can display. The Color Pallette can always be redefined and reloaded, however this usually causes the video controller to execute a hard reset which will clear the screen to black and require a screen refresh afterwards. In older video games this was often done as a game changed from one "level" to the next so that it would not interrupt the play of the game. Modern video controllers have enormous pallettes that generally never have to be redefined once the system initializes the controller during startup and if they do redefine the pallette and hard reset it often goes unnoticed to the naked eye. The color pallette is the definition of what color will be displayed for each number representing each pixel. The total number of colors that the video controller can display at a time, is the color depth.
Coppermine	Intel developmental code name for a redesign of the original Pentium III manufacturing die for the processor core. Coppermine core Pentium III's used a smaller manufacturing resolution 0.18µ which was the direct cause of its massive core speed improvements. But it also enjoyed some minor debugging by the engineers as well. Coppermine was the first P6 (Processor Sixth Generation) to return to the socket style form factor introducing the Socket 370 first in Celerons and later in mainline CPU's.
Core Duo	The Core, Core Duo, Core 2 Duo, Centrino, Centrino Duo, and Core Solo name game is a ridiculously confusing one caused by Intel's desperate attempt to hang on to successful end-user recognized names. To clarify these products we start with Pentium M: Pentium M - The simple P6-like core made with Family 15 manufacturing techniques and processor core features yields a very fast CPU - the fastest when it was released. Centrino - Market name for any PC with a Pentium M and a specific choice of Intel motherboard chipsets and a specific choice of Intel wireless network adapter. Core Duo - Physical dual core Pentium M Centrino Duo - Market name for any PC with a Pentium Core Duo and a specific choice of Intel motherboard chipsets and a specific choice of Intel wireless network adapter. Core 2 Duo - Totally new generation of processors that would have, could have, and should have been named (for lack of imagination) Pentium 5, for example. It is loosely based on the ideas born in the Pentium M but it is definitely the next generation of CPU in which the native basic core design is a dual core CPU. Core Solo - A Core 2 Duo in which one of the physical cores of the basic dual core design has been disabled, sort of the Celeron version of a Core 2 Duo, but Intel is trying to get away from the "Celeron" name because it is not as popular as they thought. Core - Intel's brand name for the Core 2 Duo's core architecture, in comparison Intel called the Pentium 4 core architecture: Intel Netburst Architecture.
Core 2 Duo	See Core Duo above.
Core Solo	See Core Duo above.
core speed	See Clock Multiplier above.
dataflow analysis	Ability of the processor core to realign instructions coming from the onboard cache and feed them to the pipeline decoders in a different order. This optimizes the execution of the instructions taking advantage of the multiple stage pipeline decoders of the P6 Family of processors. Also called "out-of-order execution."
"dead" PC	By the PC Repair Prof's definition, any PC that has no output to the display is a "dead" PC. These are the most difficult PC's to diagnose because they are not displaying any error messages to the screen.
diagonal(display)	Distance, usually in inches, from the top left corner of the display to the bottom right corner. This is the size of the display as it is advertised. For example a 19" display is not 19 inches across, it is 19 inches diagonally. To further confuse the issue, some CRT types of display have a tube that is 19 inches in diagonal but the image does not go all the way to the very edge of it. These are then advertised as 19" viewable displays. Quite often manufacturers "short change" the viewable region. Although I have not actually measured the viewable area of a flat panel display, it would not come as a shock to find some of these short changed as well.
DOS Boot Record	The first physical sector of the partition. Its location is specified in the partition tables of the MBR. It contains the DPB - Drive Parameter Block which maps the low level file system structures locations within the partition so that the OS can find and use them to access all of the files within the partition. It also contains the 2nd stage OS Boot Strap Loader which tries to load the first file of the OS itself into RAM and pass control to it during the early stages of start up. The sector ends with a boot signature so that the MBR will recognize it as a valid DBR.
DOS Boot Record error	In true versions of DOS reads: "Non-system disk or disk error, Replace the disk and press a key when ready..." In Windows 9x versions of DOS the word "Non-system" has been changed to "Invalid" in an attempt to make the message different from the Compaq BIOS Boot Strap Loader error message which they "borrowed" from the DOS Boot Strap Loader. This message is issued when the DBR which holds the 2nd stage OS Boot Strap Loader code cannot find the first OS file that needs to be loaded into RAM. For DOS/Windows9x this file is IO.SYS. For Windows NT family it is ntldr and the Volume Boot Record message reads: "NTLDR missing or corrupt, press [CTRL]+[ALT]+[DEL] to reboot"
dot pitch	Distance between the centers of the individual red-green-blue color triads in the surface of the display either a CRT or a flat panel technology. The smaller the value the sharper the images on the display will be. A dot pitch of 0.28mm is considered very blurry, 0.24mm is reasonable and 0.22mm is considered sharp.
dynamic execution	Intel terminology refering to capabilities of the core architecture starting with the P6 Family of processors. Dynamic execution consists of three separate capabilities: 1) Multiple Branch Prediction: The MMU can look ahead and pull both targets of the upcoming "if-then" statement into the cache, 2) Dataflow Analysis: "Out-of-Order Execution: pipelines can change the order in which instructions are queued and then sent into the pipeline for decoding, and 3) Speculative Execution: another "look ahead" feature that allows the alternate idle pipelines to execute a possible upcoming branch in the program, if the branch is taken, then the instructions are already done.
family(CPU)	Series of CPU's that all have similar characteristics. The x86 family, for example, are all backwards compatible in that later versions can execute program code compiled for previous versions. The 8088 was an economy version of the 8086, the true ancestor of the entire line which include the 80186 (never used in the PC), 80286 (first CPU of the IBM AT class systems, 80386 (first 32-bit CPU for the IBM AT class systems), 80486 (many firsts for the family) hence the name x86. It should be noted that Pentiums through Pentium M and Pentium 4 are all pure x86 Family members that can execute programs written specifically for any of their predecessors in this family lineage. Another example is the "P6 Family" which means all processors using the same basic core architecture. This includes: Pentium Pro, Pentium II, Pentium II Celeron, Pentium II Xeon, Pentium III, Pentium III Celeron, Pentium III Xeon, and all manufacturing resolutions and minor variations wich Intel calls "steppings".
FireWire	High speed external expansion bus developed for the Apple Computer company's personal computing products. FireWire was absorbed into the SCSI specification and is formally refered to as "Serial SCSI". FireWire uses a "daisy-chained" bus topology, maximum single cable length between devices of 4.5 meters, transfer rates of 400, 800, and 3200Mbps (not a formalized specification yet), maximum of 63 devices, full Plug-n-Play support, hot swappable device support, can supply up to 45W at 30V to a device. Extensions of FireWire allow it to use network cable Category 5e UTP - Unshielded Twisted Pair as well. FireWire allows for peer-to-peer communication so a true host controller is not needed on the bus as along as the devices have been designed to understand each other. For instance, a FireWire scanner could transfer the scan directly to a FireWire printer without having to coordinate this action through the PC.
flat panel	Form of display that does not use the CRT - Cathode Ray Tube technology borrowed from classic television design. Modern flat panels used in the PC industry are usually color LCD - Liquid Crystal Display variations, but plasma screen technology has also been used especially for larger displays.
flat screen	This is a CRT - Cathode Ray Tube display but the surface curvature has been almost completely elminated, hence reducing distortion and greatly improving image clarity as well as helping reduce reflections from the curved surface. Flat screen CRT's are the standard for modern CRT monitors for PC's but as the cost of flat panels continues to plummet, they should eventually disappear completely from the market.
high color	Term refering to a color depth component of the display resolution using 16 bits per pixel. At this color depth each pixel on the screen can be one of 65,536 different colors. High color is near photographic quality. Good graphic rendering software can interpolate original colors of a graphics file of higher color depth and render it on screen extremely well in high color.
instruction efficiency	The measure of how many clock cycles are required by the CPU processor core to complete an instruction. It is especially true of the x86 family that the instruction set includes instructions of varying length in bytes and even instructions of the same length in number of bytes, some execute much more quickly than others. Because of this, the instruction efficiency of a CPU is given as an average measurement based on very large amounts of working executable code. The 8088 had an instruction efficiency of approximately 12 clock cycles/instruction. The 80486 averaged about 1.2-2.0 clock cycles/instruction. Pentium was the first CPU to average <1 clock cycle/instruction. It is more effective to measure instruction efficiency in modern CPU's as the number of instructions they can execute per clock cycle now. The Pentium II/III cores could execute roughly 3 instructions/clock cycle.
integral	Term used to denote that the item is built in. For example, "The CPU has an integral FPU," means that the FPU - Floating Point Unit, or math coprocessor is built into the CPU core itself.
Katmai	Intel codename for the first Pentium III processor core. The Katmai introduced the core change which was relatively minimal including mainly the introduction of SSE - Streaming SIMD (Single Instruction/Multiple Data) Extensions, and some core architectural changes improving its efficiency over the Pentium II. However, Katmai was still made using the 0.25µ manufacturing resolution of the predecessors. A resolution that went all the way back to the Pentium MMX. Katmai therefore was never more than 10-20% faster than the Pentium II's which upon its released came way down in price and began selling much better than itself. Katmai would get replaced by the Coppermine core made with the new manufacturing technology of 0.18µ which within a few months doubled the core speed and was the first to surpass the 1.0GHz core speed.
Klamath	The Intel codename for the first ever Pentium II full production variation of the P6 Family of processors. While it was short-lived and replaced by the "Deschutes" core at an initial speed of 333MHz, it is a suitable term for refering to the Pentium II "regular" model versus Celerons and Xeons.
L1	Level 1 refering to the block(s) of cache closest to the processors execution core or pipelines. L1 since the 80486 has been built into the processor core itself and runs at core speed. L1 is kept backfilled from L2 cache by the MMU - Memory Management Unit, also built into the processor core starting with the 80386. L2 cache starting with the 80486 ran at FSB - Front Side Bus speed and was external to the CPU core. Starting with the P6 Family's Pentium Pro, L2 was offered at different sizes built into the core and running at core speed. After this, L2 depending on the CPU model or stepping, may either be: external or integral, FSB speed, core speed, or somewhere in between these two speeds usually measured as a fractional speed of the core. Starting with the Pentium 4 "Prescott" core, L3 cache has also been introduced. CPU's with L3, usually indicate that L2 is integral and running at a fraction of core speed. L3 cache can be internal or external and usually runs at FSB speed if external or a fraction of the core speed in internal.
L2	Level 2 refering to CPU cache. See L1 above.
L3	Level 3 refering to CPU cache. See L1 above.
manufacturing resolution	Term refering to the smallest possible single entity that can exist within an integrated circuit chip. Modern VLSI - Very Large Scale Integration manufacturing technology has reached 45 nanometer (billionths of a meter) manufacturing resolution using low wavelength laser etching techniques. To put this in perspective, the average amoeba is about 700µ across or about 700,000 nanometers. Since a transistor is made up of three elements, and requires at least one conductor element between each one, Intel can make a string of almost 4000 transistors across the length of an amoeba.
Master Boot Record	Technically the information held within the first addressable physical sector of the hard drive. But the term is used interchangeably to refer to the first physical sector of the hard drive as well. The MBR contents consist of: 1) The 1st stage OS Boot Strap Loader code, 2) the partition tables that define the actual partitions or logical containers on the hard drive (each holds a complete file system), and 3) the boot signature that the BIOS Boot Strap Loader will check to verify that the MBR is valid.
Master Boot Record error	The actual message depends on the OS that wrote the MBR code to the first physical sector of the hard drive. For DOS/Windows 9x this message is: "Missing operating system" or "Invalid partition table" Both messages are related to the same problem, the embedded 1st stage OS Boot Strap Loader code cannot find and load into RAM the first physical sector of the active partition mapped in the partition tables also located within the MBR itself. Either the partition table has been corrupted, or the contents of the first sector of the partition, in DOS/Windows9x called the DOS Boot Record, has been lost or corrupted.
Mbps	Term of measurement of serial DTR - Data Transfer Rate, meaning: Megabits per second. Because there is a unit of time in the measurement, the "Mega" must be intepreted as even millions not binary "mega" which is multiples of 1,048,576 or 220.
MBps	Term of measurement usually used for serial DTR - Data Transfer Rate, meaning: Megabytes per second. Because there is a unit of time in the measurement, the "Mega" must be intepreted as even millions not binary "mega" which is multiples of 1,048,576 or 220.
microcode	Starting with the 80486, processor core instruction decoders are called pipelines. These pipelines are themselves miniature RISC - Reduced Instruction Set Computing, computers that can be reprogrammed for their specialized task of decoding the x86 "mid-level" programming language instruction set. These pipeline instruction decoders are themselves programmed in the very low-level programming language instruction set called microcode. When a bug is identified in the basic function of the CPU's interpretation of the x86 instruction set that can be traced back to the pipeline decoder behavior, the core can be reprogrammed with new microcode. This is usually included in the latest BIOS EEPROM code update. In practically all modern systems of the "Pentium era" the motherboard BIOS EEPROM chip can be reprogrammed or "flashed" with software usually a bootable diskette or CD-ROM.
motherboard	Main circuit board or backplane of the PC. Note that the term backplane usually refers to a "passive" board that does not include a socket or slot for the microprocessor. Motherboards are also called "main board" usually by the manufacturer or "planar" the original IBM term for them. Motherboards are the first component to be considered in building a PC since they hold the single or multiple CPU socket or slot and the chipset which together determine the number of and exact models of CPU that the motherboard supports. The chipset and the physical slots provided on it also determine the type, speed, and total installable amount of RAM that the computer will support as well. The motherboard also by way of the chipset and the physical number of slots determines the types of expansion bus available and the number of expansion cards that can be installed. Finally, the motherboard can include any number of "integrated peripherals" that are already built into it, reducing the total number of expansion slots required to build a complete working PC. Integrated peripherals are usually do not have the same quality as expansion card peripherals, so integrated peripherals should only be included for peripherals of limited importance. The notable exception is the integrated SATA controller which is internally wired into either a 66MHz or a 64-bit wide PCI attachment to the PCI bus controller. Such expansion slots are rarely if ever physically included on the motherboard and these expansion cards are usually quite expensive.
multiple branch prediction	A capability of the CPU core's MMU - Memory Management Unit starting with the P6 Family of processors. Part of what Intel calls the "dynamic execution" capabilities of this family. Multiple branch prediction allows the MMU to detect an upcoming conditonal jump or "if-then-else" statement and prefetch into the CPU cache both sets of instructions. This way no matter which way the program actually jumps, both possibilities have been moved up into the high speed cache and therefore will not slow down the CPU. After the "fork in the road" has been reached, the unneeded branch is "flushed" from cache making room for the MMU to start prefetching the next upcoming set of multiple branches in the program.
netburst	Intel's marketing name for the foundational core architecture of the Family 15 products. Netburst architecture includes: 1) 5 x 20-stage pipeline decoders, 2) dual MMU's to manage transactions between main RAM and various sizes of L2's running at various speeds, 3) an unusual L1 cache consisting of two distinct sections; a "classic" 8KB or 16KB L1 holding program information, plus an "Advanced Trace Cache" that can hold up to 12K of the core microcode words), 4) a 256-bit wide data path between the L1 and the L2, and 5) 128 x 128-bit aliasable registers.
Northwood	Second major core of the Pentium 4 end-user product based on the Intel Family 15 or Netburst core architecture. Northwood included a new processor feature called HT - hyperthreading. This allows the single physical core to emulate a dual core at the hardware level (internally) Software will recognize the two cores and if capable of supporting multiple processors put them to use. Even though it is emulation code running in the microcode it still yields a 10-30% increase in overall processing performance. Northwood cores were the first Pentium 4's made with the 0.13µ manufacturing resolution and introduced the first 133MHz QDR - Quad Data Rate, FSB - Front Side Bus, at an effective speed of 533MHz and the first 200MHz QDR FSB yielding an effective speed of 800MHz.
on-die	Another term used to indicate an item that is built into the CPU core. "On-die cache," means cache RAM built into the CPU core.
parity	Technology in which an extra bit is calculated from the original data and stored or transmitted along with it. When the data is retrieved (or arrives in the case of parity transmissions) so is the parity bit. The parity bit calculation is performed again and the result is compared with the parity bit that was retrieved with the data. If the two do not match, then the recipient of the data knows that it has been corrupted. Parity alone cannot determine which bit(s) within the original data were corrupted only that it has been corrupted. Therefore parity is known as a form of EDC - Error Detection Code. Parity is useful in data transmissions because the receiver can request that the original transmitter, retransmit the data. Parity is therefore a reasonable tool for ensuring reliability in a "live" data exchange technology. However, parity proved to be relatively useless for data storage and retrieval situations even in RAM because there is no way to retrieve the original data (the receiving PC is also the original creator of the data) and so parity fell out of use in favor of ECC - Error Correction Code technologies now available for both RAM modules and regularly used in all modern hard drives. Parity can either be "Odd parity" or "Even parity" which means that in "Odd parity" the total number of "1" bits held in the original data plus the parity bit must be an odd number of them. And in even parity the total number of ones must be even. Odd parity byte, the parity bit at the far right must be set to "1" (totaling 5 ones): 0 1 1 0 0 0 1 1   1 Odd parity byte, the parity bit at the far right must be set to "0" (totaling 3 ones): 1 0 1 1 0 0 0 0   0
PCI-Express	Developed by Intel and released to the PC industry as an open architecture technology, PCI-Express is essentially "serial PCI" Logically, that is, the actual information that devices exchange over the bus is the same, but instead of using 32-bit parallel data transfer, the devices exchange data in a serial fashion. Since the bus width is much more narrow, this reduces pin count dramatically and allows for multiple "lane" expansion slots and cards that can use multiple lanes or data channels at once. A single lane runs at 2.5GHz, but PCI-Express transfers 8 bits/10 clock cycles (embedded parity) meaning a lane can transfer 250MB/sec. An x2 slot and expansion card can therefore transfer 500MB/sec. Modern PCI-Express video cards require x16 slots and use 16 lanes at a time and can therefore transfer 16 x 250MB/sec = 4GB/sec of data with the CPU and main memory.
PCI-X	Extensions of the standard parallel PCI bus including: 32-bit/66Mhz version capable of 266MB/sec, 64-bit/33MHz version also capable of 266MB/sec, 64-bit/66MHz version capable of 533MB/sec and a 64-bit/100Mhz version capable of 800MB/sec transfer rates. The controller and the expansion slots and cards never became popular with the end-user market and have a found a limited niche role in PC-based server systems. Because of the limited manufacutring volume the technology remains rather expensive. There have appeared modern revisions to the PCI-X standard supporting 133Mhz and higher leading to far greater throughput. PCI also has a "PCI Hotplug" addendum specification making it possible for manufacturers to develop hotswappable buses, expansion slots, and expansion cards. in order for this to work, the motherboard BIOS must be capable of physically turning off (and back on) all power to the slot, and the OS must be capable of communicating this to the BIOS.
Pentium 4 Extreme Edition	Basically a Pentium 4 Dual core in which each core supports HT - Hyperthreading. It should be noted that the first product was made on its own unique core die design codenamed the "Gallatin". Such a chip has two physical cores each hardware emulating two cores. The operating system capable of supporting multiple processors will recognize such a chip as four independent processors. The Gallatin core was the first Intel product to feature MMU support for and on-die L3 cache.
Pentium 4 Mobile	Also made on their own core dies, the Pentium 4 continued the Intel tradition of developing special products intended for portable PC's (laptops) Pentium 4 introduced the EIST - Enhanced Intel Speedsttep Technology which allows the CPU to step through various speeds and voltages depending on CPU usage percentages allowing it to idle down and preserve power nad reduce heat while the system does not need the full capabilities of the CPU and to throttle back up to full speed on demand of the application that suddenly needs the processing power. This is now standard in many of Intel's desktop processors as well.
Pentium 4	Main end-user product line based on the Intel Family 15 also known as the netburst core architecture.
Pentium D	The Pentium D consists of two complete Family 15 physical cores installed into a single CPU package. It is the equivalent of 2 Pentium 4 processors in one and required the FC-LGA CPU form factor and LGA775 motherboard socket which has enough pins to support the two independent cores FSB connection requirements.
Pentium Extreme Edition	A product variation of the Pentium M core. The Pentium Extreme Edition capitalizes on the popularity of the Pentium 4 Extreme Edition, but is not related except in the fact that the Pentium Extreme Edition has two physical Pentium M cores each of which is capable of HT so like its predecessor this CPU will appear to software as four independent processors.
Pentium II
Pentium III
Pentium M
Pentium MMX
Pentium Pro
Pentium
pixel
pipeline decoder
POST code
POST error
Powered USB
Prescott
S-Video
shadow mask
Slot 1
Slot 2
Socket 1
Socket 2
Socket 3
Socket 4
Socket 5
Socket 6
Socket 7
Socket 8
Socket 370
Socket 423
Socket 478
Socket J
Socket M
Socket T
speculative execution
stepping(CPU)
superscalar execution
Super Socket 7
thermal throttling
true color
Tualatin
video resolution
vertical refresh rate
voltage differential	See balanced signaling above.
Willamette	Intel code name for the first Family 15 based CPU manufacturing core which would be marketed as the Intel Pentium 4. Willamette cores began in the FC-PGA2 form factor for mounting on systems with the Socket 423 a full sized socket. However, it was the processor's form factor that caused major problems (the silicon wafer itself is exposed on the top of the ceramic square that forms the body of the chip and is easily damaged) along with some data flow bottlenecks associated with the front side bus attachments which caused Intel to quickly change the CPU form factor to the mFC-PGA478, a much smaller physical package with the IHS - Integrated Heat Spreader, a plate of metal on top of the silicon wafer that protects it from physical damage, and an improved 478 pin count increasing the data width attachments to the front side bus. Willamette debuts the Family 15 Netburst core architecture but with less than impressive performance due to the fact that it was manufactured at 0.18µ resolution along side the last of the Pentium III Tualatins made using a 0.13µ resolution. Being more efficient cores, made with better manufacturing resolutions, Tualatins were actually faster. Northwood Pentium 4's made at 0.13µ would bring a slew of CPU technologies but still fall way short of performance expectations. Pentium 4 performance would finally start to pull away only with the 90nm Prescott cores, but by that time the Pentium M project would be in full swing and compete heavily with the Prescott in the desktop as well as obliterate it in the laptop market.
Xeon	First Intel brand name used to indicate a superior CPU variant to the regular version of the product. Therefore Intel Pentium II Xeon is a superior CPU to the Intel Pentium II. Xeons were first defined as the regular version of the product equipped with a larger and faster cache. Xeons are built using a different core design and therefore have many internal architectural differences besides just the much larger and faster cache. Xeons became a separate product line all to themselves starting with the Family 15 generation of Intel Products including the Pentium 4. At that point Intel no longer marketed them as Intel Pentium 4 Xeons but simply as the Intel Xeon. As usch the product has undergone major architectural changes and is intended mainly for use in servers where it is mated to increasingly more powerful generations of chipsets especially for the purpose of dual or multiple processor based motherboards handling massive multi-threading responsibilities (needing to run many different programs simultaneously) such as network servers. Xeons in general have massive and fast caches and state-of-the-art MMU's and architectural changes including larger pin counts to allow communication with the chipset for signaling and integration with other CPU's on the same motherboard. For example, the Family 15 end-user standalone PC product, the Pentium 4 featured a 478 pin socket while the Family 15 Xeon featured a 604 pin socket.