function CheckIt(action){var i=ans[count];if(!action){if(FORM1.Q1[i].checked){alert("Correct!");}else{alert("Incorrect.");answrong++;}}else{FORM1.Q1[i].checked ? ansright++ : answrong++;}}function CheckScore(){alert("CORRECT:     " + ansright + "\nINCORRECT:  " +  answrong);}function GoBack(){var myEl = document.getElementsByTagName("p");var mySpans = document.getElementsByTagName("span");var qnum = 0;tmpstr="";count--;qnum = count + 1;if(count < 0){count=0;alert("This is the first question!");return;}tmpstr = " " + qnum + ". " + q[count];myEl[1].innerHTML=tmpstr;mySpans[0].innerHTML=a[count];mySpans[1].innerHTML=b[count];mySpans[2].innerHTML=c[count];mySpans[3].innerHTML=d[count];}function GoNext(){var myEl = document.getElementsByTagName("p");var mySpans = document.getElementsByTagName("span");var qnum=0;tmpstr="";CheckIt(1);count++;qnum=count+1;if(count > 99){TestOver();return;}tmpstr=" " + qnum + ". " + q[count];myEl[1].innerHTML=tmpstr;mySpans[0].innerHTML=a[count];mySpans[1].innerHTML=b[count];mySpans[2].innerHTML=c[count];mySpans[3].innerHTML=d[count];ClrRadios();}function TestOver(){var myEl = document.getElementsByTagName("div");var myP = document.getElementsByTagName("p");var endscores = '<span class="bold2">Correct: ' + ansright + "<br>";endscores += "Incorrect: " + answrong + "<br>";endscores += "Percentage: " + Math.floor((ansright/(ansright + answrong))*100);endscores += "%</span>";myP[1].innerHTML="TEST OVER!";myEl[0].innerHTML=endscores;FORM1.B0.disabled=1;FORM1.B1.disabled=1;FORM1.B2.disabled=1;}function Choose(){navigate("main00.pl?Z=./test/index.html");}function GoStart(){history.go(0);ClrRadios();}function ClrRadios(){FORM1.Q1[0].checked=false;FORM1.Q1[1].checked=false;FORM1.Q1[2].checked=false;FORM1.Q1[3].checked=false;}FORM1.B0.onclick=GoBack;FORM1.B1.onclick=CheckIt;FORM1.B2.onclick=GoNext;FORM1.B4.onclick=GoStart;FORM1.B5.onclick=CheckScore;FORM1.B6.onclick=Choose;var count=0;var ansright=0;var answrong=0;var q=new Array();var ans=new Array();var a=new Array();var b=new Array();var c=new Array();var d=new Array();q[0]="What is a reason a device would need an IRQ?";a[0]="A. So the CPU can signal it to get ready to receive data";b[0]="B. So the CPU can detect if it is active or inactive";c[0]="C. So it can signal the CPU to run its device driver";d[0]="D. So it can signal any other peripheral device";ans[0]="2";q[1]="What device has the IRQ with the highest priority of them all?";a[1]="A. The Master PIC";b[1]="B. The Slave PIC";c[1]="C. The Keyboard";d[1]="D. None of the above";ans[1]="3";q[2]="What device has the IRQ with the lowest priority?";a[2]="A. The keyboard";b[2]="B. The Mouse";c[2]="C. The Game Port";d[2]="D. The Parallel Port";ans[2]="3";q[3]="What IRQs are attached to the Slave PIC?";a[3]="A. 0 to 8";b[3]="B. 2 to 9";c[3]="C. 8 to 15";d[3]="D. 4 to 7";ans[3]="2";q[4]="The Interrupt Vector Table is located:";a[4]="A. Onboard the CPU";b[4]="B. Onboard the Master PIC";c[4]="C. Onboard both the Master and the Slave PICs";d[4]="D. In RAM starting at address 0000:0000";ans[4]="3";q[5]="If the CPU only has one INTR line, how can it tell what device activated its IRQ?";a[5]="A. It cannot, this is handled by the operating system";b[5]="B. The device will indicate this during the execution of the interrupt handler";c[5]="C. The PIC sends the Interrupt number on the INTR line";d[5]="D. The PIC sends the Interrupt number on the data bus";ans[5]="3";q[6]="The classic BIOS EEPROM code segment is:";a[6]="A. FFFF";b[6]="B. 0000";c[6]="C. F000";d[6]="D. Varies";ans[6]="2";q[7]="Which of the following devices have the same IRQ?";a[7]="A. AT Keyboard and serial mouse";b[7]="B. PS/2 keyboard and PS/2 mouse";c[7]="C. USB keyboard and USB mouse";d[7]="D. None of the above";ans[7]="2";q[8]="Which of the following devices have the same IRQ?";a[8]="A. COM1 and COM3";b[8]="B. LPT1 and LPT2";c[8]="C. COM2 and COM3";d[8]="D. None of the above";ans[8]="0";q[9]="Which of the following devices has the IRQ with the highest priority?";a[9]="A. Secondary ATA";b[9]="B. LPT1";c[9]="C. LPT2";d[9]="D. COM1";ans[9]="0";q[10]="Which of the following devices has the IRQ with the lowest priority?";a[10]="A. PS/2 mouse";b[10]="B. FPU";c[10]="C. Primary ATA";d[10]="D. RTC";ans[10]="2";q[11]="The IVT resides in:";a[11]="A. Conventional memory";b[11]="B. Upper memory";c[11]="C. Extended Memory";d[11]="D. High Memory";ans[11]="0";q[12]="Because legacy devices can never share IRQs, adding what device to a PC with two printers will cause a problem?";a[12]="A. Video card";b[12]="B. Modem";c[12]="C. Slave on the Primary ATA Channel";d[12]="D. None of the above";ans[12]="3";q[13]="Changing a PS/2 mouse to a serial mouse will:";a[13]="A. Free an IRQ and cost a COM port";b[13]="B. Cost a COM port";c[13]="C. Free an IRQ";d[13]="D. None of the above";ans[13]="0";q[14]="Changing a PS/2 mouse to a USB mouse will:";a[14]="A. Free an IRQ and cost a COM port";b[14]="B. Cost a COM port";c[14]="C. Free an IRQ";d[14]="D. None of the above";ans[14]="2";q[15]="You install a new PCI video card on a legacy system with a SCSI controller. It boots through BIOS but crashes shortly after the Windows splash screen because:";a[15]="A. The drivers are corrupt or not installed yet";b[15]="B. The PCI drivers conflict with the legacy devices";c[15]="C. The video card tries to use IRQ11 in graphics mode";d[15]="D. None of the above";ans[15]="2";q[16]="List the following IRQs in order of priority:";a[16]="A. 7,8,9,10";b[16]="B. 8,7,9,10";c[16]="C. 9,10,7,8";d[16]="D. 8,9,10,7";ans[16]="3";q[17]="List the following devices by IRQ priority";a[17]="A. RTC, FPU, COM2, COM1";b[17]="B. COM2, COM1, RTC, FPU";c[17]="C. COM1, COM2, FPU, RTC";d[17]="D. RTC, COM1, FPU, COM2";ans[17]="0";q[18]="I/O addresses provide the ability for:";a[18]="A. The CPU to signal the device it is ready";b[18]="B. The device to signal the CPU it is ready";c[18]="C. The CPU and the device to exchange data";d[18]="D. None of the above";ans[18]="2";q[19]="The base I/O address of the RTC is:";a[19]="A. 40h";b[19]="B. 60h";c[19]="C. 70h";d[19]="D. C0h";ans[19]="2";q[20]="The base I/O address of the keyboard is:";a[20]="A. 40h";b[20]="B. 60h";c[20]="C. 70h";d[20]="D. C0h";ans[20]="1";q[21]="8-bit I/O addresses are usually used by:";a[21]="A. Members of the motherboard chipset";b[21]="B. I/O peripheral devices";c[21]="C. Storage peripheral devices";d[21]="D. There is no preference";ans[21]="0";q[22]="A read-only I/O address is also called a";a[22]="A. Command port used only to send commands to the device";b[22]="B. Status port used only to read status messages from te device";c[22]="C. Data port used to send or receive data to or from the device";d[22]="D. There is no such distinction in I/O addresses";ans[22]="1";q[23]="The base I/O address of the primary ATA is:";a[23]="A. F0h";b[23]="B. 170h";c[23]="C. 1F0h";d[23]="D. 3F0h";ans[23]="2";q[24]="Which of the following devices use the same I/O addresses?";a[24]="A. AT keyboard and PS/2 mouse";b[24]="B. AT keyboard and serial mouse";c[24]="C. PS/2 keyboard and USB mouse";d[24]="D. None of the above";ans[24]="0";q[25]="Which of the following devices has an 8-bit base I/O address?";a[25]="A. FPU";b[25]="B. FDC";c[25]="C. LPT1";d[25]="D. COM1";ans[25]="0";q[26]="Which of the following devices has a 16-bit base I/O address?";a[26]="A. PS/2 mouse";b[26]="B. RTC";c[26]="C. System Timer";d[26]="D. Primary ATA";ans[26]="3";q[27]="Which of the following devices has a standard I/O address but no IRQ?";a[27]="A. LPT2";b[27]="B. math coprocessor";c[27]="C. CMOS RAM chip";d[27]="D. Legacy game port";ans[27]="3";q[28]="What is the base I/O address of COM1?";a[28]="A. 278h";b[28]="B. 2F8h";c[28]="C. 3E0h";d[28]="D. 3F8h";ans[28]="3";q[29]="What is the base I/O address of LPT1?";a[29]="A. 378h";b[29]="B. 3E8h";c[29]="C. 3F0h";d[29]="D. 3F8h";ans[29]="0";q[30]="What is the base I/O address of COM2?";a[30]="A. 278h";b[30]="B. 2F8h";c[30]="C. 3E0h";d[30]="D. 3F8h";ans[30]="1";q[31]="What is the base I/O address of COM3?";a[31]="A. 378h";b[31]="B. 3E8h";c[31]="C. 3F0h";d[31]="D. 3F8h";ans[31]="1";q[32]="What is the base I/O address of the secondary ATA channel?";a[32]="A. 100h";b[32]="B. 170h";c[32]="C. 278h";d[32]="D. 3F0h";ans[32]="1";q[33]="What is the base I/O address of LPT2?";a[33]="A. 100h";b[33]="B. 170h";c[33]="C. 278h";d[33]="D. 3F0h";ans[33]="2";q[34]="What is the correct configuration of COM4?";a[34]="A. IRQ3 and I/O of 3E8h";b[34]="B. IRQ3 and I/O of 2E8h";c[34]="C. IRQ4 and I/O of 3E8h";d[34]="D. IRQ4 and I/O of 2E8h";ans[34]="1";q[35]="What is the correct configuration of COM3?";a[35]="A. IRQ3 and I/O of 3E8h";b[35]="B. IRQ3 and I/O of 2E8h";c[35]="C. IRQ4 and I/O of 3E8h";d[35]="D. IRQ4 and I/O of 2E8h";ans[35]="2";q[36]="What is the correct configuration of LPT1?";a[36]="A. IRQ5 and I/O of 278h";b[36]="B. IRQ7 and I/O of 278h";c[36]="C. IRQ5 and I/O of 378h";d[36]="D. IRQ7 and I/O of 378h";ans[36]="3";q[37]="What is the correct configuration of LPT2?";a[37]="A. IRQ5 and I/O of 278h";b[37]="B. IRQ7 and I/O of 278h";c[37]="C. IRQ5 and I/O of 378h";d[37]="D. IRQ7 and I/O of 378h";ans[37]="0";q[38]="What is the correct configuration of the math coprocessor?";a[38]="A. IRQ13 and I/O of F0h";b[38]="B. No IRQ and I/O of F0h";c[38]="C. IRQ13 and no I/O";d[38]="D. None of the above";ans[38]="0";q[39]="The function of the DMA chip is to manage high speed data transfers:";a[39]="A. from the CPU to RAM";b[39]="B. from RAM to the CPU";c[39]="C. between devices and the CPU";d[39]="D. between devices and RAM";ans[39]="3";q[40]="The DMA controller is now becoming deprecated because:";a[40]="A. No more devices are being designed to use it";b[40]="B. It is tied to the inefficient and slow ISA bus";c[40]="C. Modern peripherals include their own faster versions";d[40]="D. It is not becoming deprecated yet";ans[40]="1";q[41]="How many 16-bit DMA channels are available (no standard assignments)?";a[41]="A. 2";b[41]="B. 3";c[41]="C. 4";d[41]="D. None, they are all assigned";ans[41]="1";q[42]="How many 8-bit DMA channels are available (no standard assignments)?";a[42]="A. 2";b[42]="B. 3";c[42]="C. 4";d[42]="D. None, they are all assigned";ans[42]="0";q[43]="The CPU became so fast that it could execute program code to accomplish the DMA chip function faster, this is called:";a[43]="A. Ultra DMA";b[43]="B. PIO";c[43]="C. DIME - Direct Integrated Memory Execution";d[43]="D. The CPU never becam faster than the DMA chip";ans[43]="1";q[44]="What device uses DMA2?";a[44]="A. FPU";b[44]="B. FDC";c[44]="C. ATA";d[44]="D. LPT";ans[44]="1";q[45]="What device depending on its mode could use DMA3?";a[45]="A. FPU";b[45]="B. FDC";c[45]="C. ATA";d[45]="D. LPT";ans[45]="3";q[46]="What device used an 8-bit DMA but this is now obsolete?";a[46]="A. FPU";b[46]="B. FDC";c[46]="C. ATA";d[46]="D. LPT";ans[46]="2";q[47]="Which modern device might use DMA0 and DMA5?";a[47]="A. SCSI controller";b[47]="B. ATA controller";c[47]="C. Video card";d[47]="D. Sound card";ans[47]="3";q[48]="Which of the following is an 8-bit DMA channel?";a[48]="A. 3";b[48]="B. 4";c[48]="C. 5";d[48]="D. 6";ans[48]="0";q[49]="Which 16-bit DMA channel cannot be used by any device?";a[49]="A. 3";b[49]="B. 4";c[49]="C. 5";d[49]="D. 6";ans[49]="1";q[50]="The AT motherboard added how many new DMA controllers?";a[50]="A. None, only wired new 16-bit channels to the existing chip";b[50]="B. One, added both the 8-bit and the 16-bit channels";c[50]="C. One, added only the 16-bit channels";d[50]="D. Two, one added the 8-bit channels, the other added the 16-bit channels";ans[50]="2";q[51]="Why was the original IBM PC given a DMA controller?";a[51]="A. The DMA chip can transfer data faster than the 8088";b[51]="B. The DMA chip offloads this work allowing the CPU to continue executing code";c[51]="C. The DMA chip is the only way for devices to transfer data to/from RAM";d[51]="D. There was no DMA chip in the original PC, it was added in the IBM AT";ans[51]="0";q[52]="The correct configuration for LPT2 in ECP mode is:";a[52]="A. IRQ5, I/O 378h, DMA2";b[52]="B. IRQ7, I/O 278h, DMA2";c[52]="C. IRQ5, I/O 278h, DMA3";d[52]="D. IRQ7, I/O 378h, DMA3";ans[52]="2";q[53]="What common modern peripheral can make good use of DMAs?";a[53]="A. ATA";b[53]="B. RTC";c[53]="C. Video card";d[53]="D. Sound card";ans[53]="3";q[54]="Sound cards use the 8-bit DMA channel for:";a[54]="A. Recording";b[54]="B. Playback";c[54]="C. Digitized wave files";d[54]="D. MIDI";ans[54]="3";q[55]="Sound cards use the 16-bit DMA channel for:";a[55]="A. Recording";b[55]="B. Playback";c[55]="C. Digitized wave files";d[55]="D. MIDI";ans[55]="2";q[56]="During the POST, BIOS can assign the parallel port mode, this can cause conflicts with:";a[56]="A. the automatically assigned I/O address";b[56]="B. the automatically assigned IRQ";c[56]="C. the automatically assigned DMA";d[56]="D. The parallel port mode change will cause no system resource conflicts";ans[56]="2";q[57]="Which 16-bit DMA is used for communication between the master and slave DMA chips?";a[57]="A. 3";b[57]="B. 4";c[57]="C. 5";d[57]="D. 7";ans[57]="1";q[58]="The master DMA controller uses what IRQ?";a[58]="A. 0";b[58]="B. 1";c[58]="C. 2";d[58]="D. It does not use one";ans[58]="3";q[59]="The master DMA controller uses what base I/O address?";a[59]="A. 0x0";b[59]="B. 0x20";c[59]="C. 0x40";d[59]="D. 0xA0";ans[59]="0";q[60]="Parallel ports usually run faster in ECP mode because:";a[60]="A. ECP devices are more modern than EPP, or SPP devices";b[60]="B. Using this mode requires superior cables and connectors";c[60]="C. It uses a DMA to facilitate high speed transfer directly to/from RAM";d[60]="D. It is no faster than EPP";ans[60]="2";q[61]="The standard peripheral component behind the serial port is the:";a[61]="A. ISA bus controller chip";b[61]="B. Parallel port controller chip";c[61]="C. Programmable Interrupt Controller chip";d[61]="D. Universal Asynchronous Receive/Transmit chip";ans[61]="3";q[62]="The original parallel port could only receive ___ bits at a time from external devices.";a[62]="A. 1";b[62]="B. 4";c[62]="C. 8";d[62]="D. 16";ans[62]="1";q[63]="The original parallel port was upgraded to full bidirectional capability in the:";a[63]="A. IBM XT";b[63]="B. IBM AT";c[63]="C. IBM PS/2";d[63]="D. Industry standard ATX specification";ans[63]="2";q[64]="Modern BIOS often refers to standard bidirectional parallel port mode as:";a[64]="A. Bidirectional mode";b[64]="B. EPP mode";c[64]="C. ECP mode";d[64]="D. SPP mode";ans[64]="3";q[65]="The I/O throughput of SPP is roughly";a[65]="A. 50KB/sec";b[65]="B. 150KB/sec";c[65]="C. 500KB/sec";d[65]="D. None of the above";ans[65]="1";q[66]="The I/O throughput of EPP is roughly";a[66]="A. 50KB/sec";b[66]="B. 150KB/sec";c[66]="C. 500KB/sec";d[66]="D. None of the above";ans[66]="2";q[67]="Serial ports have been rendered deprecated by what modern technology?";a[67]="A. ATA";b[67]="B. UART";c[67]="C. DVI";d[67]="D. USB";ans[67]="3";q[68]="Which of the following is a feature of USB?";a[68]="A. Maximum of 127 devices";b[68]="B. Star topology";c[68]="C. Provides +5VDC to devices";d[68]="D. All of the above";ans[68]="3";q[69]="Which communication signaling method is used by USB?";a[69]="A. Wireless";b[69]="B. Single Ended";c[69]="C. Unbalanced";d[69]="D. Voltage Differential";ans[69]="3";q[70]="Which encoding method for data in the signal is used by USB?";a[70]="A. Manchester code";b[70]="B. RLL";c[70]="C. MFM";d[70]="D. NRZI";ans[70]="3";q[71]="Which of the following is a feature of FireWire but not USB?";a[71]="A. Fully Plug-n-Play";b[71]="B. Supports dozens of external devices";c[71]="C. Supports speeds greater than standard network devices";d[71]="D. Does not require a host adapter on the bus";ans[71]="3";q[72]="The maximum single cable length in USB is:";a[72]="A. 1M";b[72]="B. 3M";c[72]="C. 4.5M";d[72]="D. 5M";ans[72]="3";q[73]="The maximum single cable length in FireWire is:";a[73]="A. 1M";b[73]="B. 3M";c[73]="C. 4.5M";d[73]="D. 5M";ans[73]="2";q[74]="FireWire has been incorporated as a subset of what other technology?";a[74]="A. ATA-8 (SATA)";b[74]="B. SCSI (SPI3)";c[74]="C. USB 2.0";d[74]="D. None of the above";ans[74]="1";q[75]="A USB unpowered hub may only deliver how much current to any one device?";a[75]="A. 100mA";b[75]="B. 400mA";c[75]="C. 500mA";d[75]="D. Any as long as it requests it in increments of 100mA at a time";ans[75]="1";q[76]="A USB host controller may only deliver how much current to any one device?";a[76]="A. 100mA";b[76]="B. 400mA";c[76]="C. 500mA";d[76]="D. Any as long as it requests it in increments of 100mA at a time";ans[76]="2";q[77]="The maximum DTR of USB 1.1 is:";a[77]="A. 1.2Mbps";b[77]="B. 1.5Mbps";c[77]="C. 1.2MBps";d[77]="D. 1.5MBps";ans[77]="3";q[78]="The DTR of USB &quot;Lo channel&quot; is:";a[78]="A. 1.2Mbps";b[78]="B. 1.5Mbps";c[78]="C. 1.2MBps";d[78]="D. 1.5MBps";ans[78]="1";q[79]="The maximum DTR of USB &quot;Full speed channel&quot; is:";a[79]="A. 12Mbps";b[79]="B. 15Mbps";c[79]="C. 60MBps";d[79]="D. None of the above";ans[79]="0";q[80]="The maximum DTR of USB &quot;Hi speed channel&quot; is:";a[80]="A. 12Mbps";b[80]="B. 15Mbps";c[80]="C. 60MBps";d[80]="D. None of the above";ans[80]="2";q[81]="The first protected mode CPU for the PC industry was the:";a[81]="A. 80286";b[81]="B. 80386DX";c[81]="C. 80486DX";d[81]="D. Pentium";ans[81]="0";q[82]="The first full 32-bit CPU for the PC industry was the:";a[82]="A. 80286";b[82]="B. 80386DX";c[82]="C. 80486DX";d[82]="D. Pentium";ans[82]="1";q[83]="The first CPU for the PC industry with a clock multiplied core was the:";a[83]="A. 80286";b[83]="B. 80386DX";c[83]="C. 80486DX";d[83]="D. Pentium";ans[83]="2";q[84]="The first CPU for the PC industry with dual 16KB L1 cache was the:";a[84]="A. Pentium";b[84]="B. Pentium MMX";c[84]="C. Pentium Pro";d[84]="D. Pentium II";ans[84]="1";q[85]="The first full production Intel sixth generation processor for the PC industry was the:";a[85]="A. Pentium";b[85]="B. Pentium MMX";c[85]="C. Pentium Pro";d[85]="D. Pentium II";ans[85]="3";q[86]="The first economy model Intel Pentium for the PC industry was a variant of the:";a[86]="A. Pentium";b[86]="B. Pentium MMX";c[86]="C. Pentium Pro";d[86]="D. Pentium II";ans[86]="3";q[87]="The first slot mounted Intel processor for the PC industry was the:";a[87]="A. Pentium";b[87]="B. Pentium MMX";c[87]="C. Pentium Pro";d[87]="D. Pentium II";ans[87]="3";q[88]="Which variant has the faster L2 cache?";a[88]="A. Pentium II &quot;Klamath&quot;";b[88]="B. Pentium II Celeron";c[88]="C. Pentium II Celeron A";d[88]="D. Pentium II w/MMX";ans[88]="2";q[89]="Which processor introduced Family 15 CPUs for end-user systems?";a[89]="A. Pentium III &quot;Tualatin&quot;";b[89]="B. Pentium 4 &quot;Willamette&quot;";c[89]="C. Pentium 4 &quot;Northwood&quot;";d[89]="D. Pentium 4 &quot;Mobile&quot;";ans[89]="1";q[90]="Which processor is part of what Intel markets as &quot;Intel Centrino Inside&quot;?";a[90]="A. Pentium III &quot;Tualatin&quot;";b[90]="B. Pentium D";c[90]="C. Pentium 4 &quot;Mobile&quot;";d[90]="D. Pentium M";ans[90]="3";q[91]="Which processor was the first dual physical core Family 15 product?";a[91]="A. Pentium III &quot;Tualatin&quot;";b[91]="B. Pentium D";c[91]="C. Pentium 4 &quot;Mobile&quot;";d[91]="D. Pentium M";ans[91]="1";q[92]="A dual physical core Pentium M is called the:";a[92]="A. Pentium M Duo";b[92]="B. Pentium D";c[92]="C. Pentium Core Duo";d[92]="D. None of the above";ans[92]="2";q[93]="What technology is a single physical core emulating a dual core?";a[93]="A. VT";b[93]="B. EIST";c[93]="C. ATC";d[93]="D. HT";ans[93]="3";q[94]="What technology allows a dual core to function completely independent of each other?";a[94]="A. VT";b[94]="B. EIST";c[94]="C. ATC";d[94]="D. HT";ans[94]="0";q[95]="Which of the following technologies is part of the Intel Family 15 core?";a[95]="A. 256-bit data bus pathway to cache";b[95]="B. 128 x 128-bit aliasable registers";c[95]="C. 5 x 20-stage pipeline decoders";d[95]="D. All of the above";ans[95]="3";q[96]="Which of the following technologies was not developed for the Family 15 product line?";a[96]="A. SSE";b[96]="B. QDR FSB";c[96]="C. XD";d[96]="D. EM64T";ans[96]="0";q[97]="Which of the following technologies represents the first fundamental change to the function of protected mode?";a[97]="A. SSE";b[97]="B. QDR FSB";c[97]="C. XD";d[97]="D. EM64T";ans[97]="2";q[98]="Which of the following technologies greatly improves the DTR of the CPU?";a[98]="A. SSE";b[98]="B. QDR FSB";c[98]="C. XD";d[98]="D. EM64T";ans[98]="1";q[99]="What was the first end-user Intel processor that could run 64-bit software?";a[99]="A. Pentium III &quot;Tualatin&quot;";b[99]="B. Pentium 4 &quot;Northwood&quot;";c[99]="C. Pentium 4 &quot;Prescott&quot;";d[99]="D. None of these can run 64-bit software";ans[99]="2";