function CheckIt(action){var i=ans[count];if(!action){if(FORM1.Q1[i].checked){alert("Correct!");}else{alert("Incorrect.");answrong++;}}else{FORM1.Q1[i].checked ? ansright++ : answrong++;}}function CheckScore(){alert("CORRECT:     " + ansright + "\nINCORRECT:  " +  answrong);}function GoBack(){var myEl = document.getElementsByTagName("p");var mySpans = document.getElementsByTagName("span");var qnum = 0;tmpstr="";count--;qnum = count + 1;if(count < 0){count=0;alert("This is the first question!");return;}tmpstr = " " + qnum + ". " + q[count];myEl[1].innerHTML=tmpstr;mySpans[0].innerHTML=a[count];mySpans[1].innerHTML=b[count];mySpans[2].innerHTML=c[count];mySpans[3].innerHTML=d[count];}function GoNext(){var myEl = document.getElementsByTagName("p");var mySpans = document.getElementsByTagName("span");var qnum=0;tmpstr="";CheckIt(1);count++;qnum=count+1;if(count > 99){TestOver();return;}tmpstr=" " + qnum + ". " + q[count];myEl[1].innerHTML=tmpstr;mySpans[0].innerHTML=a[count];mySpans[1].innerHTML=b[count];mySpans[2].innerHTML=c[count];mySpans[3].innerHTML=d[count];ClrRadios();}function TestOver(){var myEl = document.getElementsByTagName("div");var myP = document.getElementsByTagName("p");var endscores = '<span class="bold2">Correct: ' + ansright + "<br>";endscores += "Incorrect: " + answrong + "<br>";endscores += "Percentage: " + Math.floor((ansright/(ansright + answrong))*100);endscores += "%</span>";myP[1].innerHTML="TEST OVER!";myEl[0].innerHTML=endscores;FORM1.B0.disabled=1;FORM1.B1.disabled=1;FORM1.B2.disabled=1;}function Choose(){navigate("main00.pl?Z=./test/index.html");}function GoStart(){history.go(0);ClrRadios();}function ClrRadios(){FORM1.Q1[0].checked=false;FORM1.Q1[1].checked=false;FORM1.Q1[2].checked=false;FORM1.Q1[3].checked=false;}FORM1.B0.onclick=GoBack;FORM1.B1.onclick=CheckIt;FORM1.B2.onclick=GoNext;FORM1.B4.onclick=GoStart;FORM1.B5.onclick=CheckScore;FORM1.B6.onclick=Choose;var count=0;var ansright=0;var answrong=0;var q=new Array();var ans=new Array();var a=new Array();var b=new Array();var c=new Array();var d=new Array();q[0]="The original IBM PC had an ISA bus at what data width and what speed?";a[0]="A. 8-bit at 4.77Mhz";b[0]="B. 16-bit at 4.77Mhz";c[0]="C. 8-bit at 8.33Mhz";d[0]="D. 16-bit at 8.33Mhz";ans[0]="0";q[1]="The main function of the CPU is:";a[1]="A. Fetch, decode and execute machine language instructions";b[1]="B. Floating point decimal mathematical operations";c[1]="C. Translate ASCII codes into associated bitmaps";d[1]="D. Provide the system with the low level 16-bit device drivers";ans[1]="0";q[2]="Name 3 software components of the BIOS:";a[2]="A. POST";b[2]="B. Boot strap loader";c[2]="C. Setup Utility";d[2]="D. All of the above";ans[2]="3";q[3]="The component that stores the hardware configuration settings is the:";a[3]="A. EEPROM";b[3]="B. CMOS RAM";c[3]="C. SRAM cache";d[3]="D. The hard drive";ans[3]="1";q[4]="The program code on the EEPROM contains:";a[4]="A. The Operating System";b[4]="B. BIOS";c[4]="C. POST";d[4]="D. Hardware Configuration Settings";ans[4]="1";q[5]="The first step of the boot sequence of the IBM PC is:";a[5]="A. POST";b[5]="B. BIOS boot strap loader";c[5]="C. IO.SYS";d[5]="D. COMMAND.COM";ans[5]="0";q[6]="The IBM AT introduced ISA redesigned at what data width and what speed?";a[6]="A. 8-bit at 4.77Mhz";b[6]="B. 16-bit at 4.77Mhz";c[6]="C. 8-bit at 8.33Mhz";d[6]="D. 16-bit at 8.33Mhz";ans[6]="3";q[7]="Which of the following is not a system resource?";a[7]="A. RAM";b[7]="B. CMOS";c[7]="C. IRQ";d[7]="D. DMA";ans[7]="1";q[8]="Which standard peripheral does not use any expansion bus system resources?";a[8]="A. The ATA controller";b[8]="B. The Floppy drive controller";c[8]="C. The Serial ports";d[8]="D. the Video controller";ans[8]="3";q[9]="What is the throughput of a VESA slot on a 33Mhz FSB system?";a[9]="A. 33.3MB/sec";b[9]="B. 66.6MB/sec";c[9]="C. 100MB/sec";d[9]="D. 133MB/sec";ans[9]="3";q[10]="The original ISA bus had a theoretical maximum data throughput of:";a[10]="A. 4.77Mbps";b[10]="B. 4.77MB/sec";c[10]="C. 4.77Mhz";d[10]="D. 4.77Bps";ans[10]="1";q[11]="The standard PCI bus has a maximum data throughput of:";a[11]="A. 33MB/sec";b[11]="B. 66MB/sec";c[11]="C. 133MB/sec";d[11]="D. 266MB/sec";ans[11]="2";q[12]="The AGP slot provides video cards with a maximum data throughput of:";a[12]="A. 33MB/sec";b[12]="B. 66MB/sec";c[12]="C. 133MB/sec";d[12]="D. 266MB/sec";ans[12]="3";q[13]="PCI-X is a special adaptation of the PCI found found on high end workstations and servers that features:";a[13]="A. 100Mhz bus speed";b[13]="B. 64-bit data bus width";c[13]="C. 800MB/sec throughput";d[13]="D. All of the above";ans[13]="3";q[14]="AGP 4x is a modified AGP slot that requires:";a[14]="A. Hardware support in the motherboard";b[14]="B. BIOS support";c[14]="C. Hardware support in the video card";d[14]="D. All of the above";ans[14]="3";q[15]="AGP 4x has a maximum data throughput of:";a[15]="A. 266MB/sec";b[15]="B. 533MB/sec";c[15]="C. 1066MB/sec";d[15]="D. 2133MB/sec";ans[15]="2";q[16]="cache is:";a[16]="A. A group of wires each of which carries a significant digit of a single large binary number";b[16]="B. Data is moved forward from a slower storage technology into this";c[16]="C. Set of circuits that interface the CPU itself with the rest of the computer system";d[16]="D. An 8-bit binary number";ans[16]="1";q[17]="codec is:";a[17]="A. Bit stored with the data that forces the number of ones to be either odd or even";b[17]="B. Software that contains the algorithm to compress or decompress a data stream on-the-fly";c[17]="C. Any system that inputs data processes the data and outputs information";d[17]="D. The main circuit board of the PC to which the CPU is attached";ans[17]="1";q[18]="parity is:";a[18]="A. Bit stored with the data that forces the number of ones to be either odd or even";b[18]="B. Software that contains the algorithm to compress or decompress a data stream on-the-fly";c[18]="C. Any system that inputs data processes the data and outputs information";d[18]="D. The main circuit board of the PC to which the CPU is attached";ans[18]="0";q[19]="protected mode is:";a[19]="A. Any technology that does NOT adhere to any industry standards";b[19]="B. Storage cell in which the system can hold a number and do math/logic operations on it";c[19]="C. When an x86 CPU is running 16-bit code and using the 16-bit memory addressing scheme";d[19]="D. When an x86 CPU other than the 8088 is using its native memory addressing scheme";ans[19]="3";q[20]="register is:";a[20]="A. Any technology that does NOT adhere to any industry standards";b[20]="B. Storage cell in which the system can hold a number and do math/logic operations on it";c[20]="C. When an x86 CPU is running 16-bit code and using the 16-bit memory addressing scheme";d[20]="D. When an x86 CPU other than the 8088 is using its native memory addressing scheme";ans[20]="1";q[21]="real mode is:";a[21]="A. Any technology that does NOT adhere to any industry standards";b[21]="B. Storage cell in which the system can hold a number and do math/logic operations on it";c[21]="C. When an x86 CPU is running 16-bit code and using the 16-bit memory addressing scheme";d[21]="D. When an x86 CPU other than the 8088 is using its native memory addressing scheme";ans[21]="2";q[22]="Which type of chip holds the BIOS machine language program code?";a[22]="A. RAM";b[22]="B. ROM";c[22]="C. CMOS";d[22]="D. CPU";ans[22]="1";q[23]="Which of the following is not a part of the BIOS software components?";a[23]="A. POST";b[23]="B. CMOS";c[23]="C. Setup Utility";d[23]="D. Boot strap loader";ans[23]="1";q[24]="Which of the following devices has no built in support in DOS?";a[24]="A. PS/2 Keyboard";b[24]="B. PS/2 Mouse";c[24]="C. Serial Ports";d[24]="D. Parallel Ports";ans[24]="1";q[25]="When a SIMM is called 8-bit this refers to:";a[25]="A. The amount of data that the SIMM can store";b[25]="B. The width of the SIMMs data bus";c[25]="C. The width of the SIMMs address bus";d[25]="D. The amount of parity information stored on the SIMM";ans[25]="1";q[26]="Odd parity memory:";a[26]="A. Stores an extra bit with each byte which makes the total number of 1s odd";b[26]="B. Stores an extra bit with each byte which makes the total number of 0s odd";c[26]="C. Stores bytes in odd numbered pairs in order to detect errors";d[26]="D. Stores odd numbers of bytes in order to detect errors";ans[26]="0";q[27]="A 486 based PC would need how many 30-pin SIMMs to fill a memory bank (and work)?";a[27]="A. 1";b[27]="B. 2";c[27]="C. 3";d[27]="D. 4";ans[27]="3";q[28]="How many standard IRQs are there on the AT motherboard?";a[28]="A. 1";b[28]="B. 8";c[28]="C. 15";d[28]="D. 16";ans[28]="3";q[29]="Conventional Memory ranges from:";a[29]="A. Very low addresses up to 640KB";b[29]="B. Very high addresses down to 640KB";c[29]="C. The first 1KB of addresses starting at address zero";d[29]="D. All memory above the 1MB address";ans[29]="0";q[30]="Upper Memory ranges from:";a[30]="A. Very low addresses up to 640KB";b[30]="B. Very high addresses down to 640KB";c[30]="C. The first 1KB of addresses starting at address zero";d[30]="D. All memory above the 1MB address";ans[30]="1";q[31]="What was the clock speed of the 8088?";a[31]="A. 4.77Khz";b[31]="B. 477Khz";c[31]="C. 4770Khz";d[31]="D. 47700Khz";ans[31]="2";q[32]="What was the problem with the protected mode of the 80286?";a[32]="A. Could only enter protected mode by resetting";b[32]="B. Could only exit protected mode by resetting";c[32]="C. Could reset to either real or protected mode but not change between them";d[32]="D. It had no protected mode problems, that was the 80186";ans[32]="1";q[33]="What was the first CPU to feature an onboard cache MMU?";a[33]="A. 80286";b[33]="B. 80386";c[33]="C. 80486";d[33]="D. Pentium";ans[33]="2";q[34]="What technology did the CPU in the previous question introduce for laptops?";a[34]="A. SIMM";b[34]="B. SMM";c[34]="C. SMP";d[34]="D. SIPP";ans[34]="1";q[35]="What was the first full 32-bit CPU for the IBM PC industry?";a[35]="A. 80286";b[35]="B. 80386";c[35]="C. 80486";d[35]="D. Pentium";ans[35]="1";q[36]="Which statement is true concerning the difference between the 486DX and the 486SX?";a[36]="A. The SX has no FPU";b[36]="B. The DX has a wider data bus";c[36]="C. The SX has a narrower address bus";d[36]="D. The SX has a similar pinout to the 80386";ans[36]="0";q[37]="What was the first processor to feature a clock multiplied core?";a[37]="A. 80286";b[37]="B. 80386";c[37]="C. 80486";d[37]="D. Pentium";ans[37]="2";q[38]="What was the first processor to feature a pipeline decoder?";a[38]="A. 80286";b[38]="B. 80386";c[38]="C. 80486";d[38]="D. Pentium";ans[38]="2";q[39]="An 8088 averages ____ clock cycles to complete the execution of an instruction?";a[39]="A. Between 1 and 2";b[39]="B. Between 2.25 and 4.5";c[39]="C. About 4.5";d[39]="D. About 12";ans[39]="3";q[40]="An 80286 averages ____ clock cycles to complete the execution of an instruction?";a[40]="A. Between 1 and 2";b[40]="B. Between 2.25 and 4.5";c[40]="C. About 4.5";d[40]="D. About 12";ans[40]="2";q[41]="What memory technology is mostly associated with 72-pin SIMMs?";a[41]="A. TTL DRAM";b[41]="B. EDO";c[41]="C. SDRAM";d[41]="D. DDR";ans[41]="1";q[42]="What memory technology is mostly associated with 30-pin SIMMs?";a[42]="A. TTL DRAM";b[42]="B. EDO";c[42]="C. SDRAM";d[42]="D. DDR";ans[42]="0";q[43]="DOS and the BIOS are called 16-bit code because:";a[43]="A. They are 16-bits in size";b[43]="B. They are stored entirely as 16-bit numbers";c[43]="C. They are encrypted using a 16-bit algorithm";d[43]="D. They can do math or logic on 16-bit numbers in the CPU registers";ans[43]="3";q[44]="The main function of the FPU is:";a[44]="A. Fetch, decode and execute machine language instructions";b[44]="B. Floating point decimal mathematical operations";c[44]="C. Translate ASCII codes into associated bitmaps";d[44]="D. Provide the system with the low level 16-bit device drivers";ans[44]="1";q[45]="The main function of the BIOS is:";a[45]="A. Fetch, decode and execute machine language instructions";b[45]="B. Floating point decimal mathematical operations";c[45]="C. Translate ASCII codes into associated bitmaps";d[45]="D. Provide the system with the low level 16-bit device drivers";ans[45]="3";q[46]="Name a software component of the BIOS?";a[46]="A. Cache";b[46]="B. A JMP instruction";c[46]="C. 16-bit device drivers";d[46]="D. text mode video array";ans[46]="2";q[47]="Which of the following is not a part of the BIOS hardware components?";a[47]="A. POST";b[47]="B. CMOS";c[47]="C. ROM";d[47]="D. Battery";ans[47]="0";q[48]="What are the two sizes of SIMM?";a[48]="A. 32-pin/8-bit and 70-pin/32-bit";b[48]="B. 30-pin/8-bit and 72-pin/32-bit";c[48]="C. 30-pin/8-bit and 70-pin/16-bit";d[48]="D. 32-pin/8-bit and 72-pin/16-bit";ans[48]="1";q[49]="The boot sequence of the IBM PC proceeds as:";a[49]="A. POST, BIOS boot strap loader, COMMAND.COM, IO.SYS";b[49]="B. POST, IO.SYS, CONFIG.SYS, BIOS Boot strap loader, COMMAND.COM";c[49]="C. BIOS Boot strap loader, IO.SYS, CONFIG.SYS, COMMAND.COM, POST";d[49]="D. POST, BIOS Boot strap loader, IO.SYS, CONFIG.SYS, COMMAND.COM";ans[49]="3";q[50]="What three common modern devices do not have any support built in to IO.SYS?";a[50]="A. Parallel port, ATAPI devices, serial ports";b[50]="B. Parallel port, USB ports, mouse";c[50]="C. ATAPI devices, serial ports, USB ports";d[50]="D. ATAPI devices, USB ports, mouse";ans[50]="3";q[51]="A Pentium (I) based PC would need how many 72-pin SIMMs to fill a memory bank?";a[51]="A. 1";b[51]="B. 2";c[51]="C. 3";d[51]="D. 4";ans[51]="1";q[52]="Extended memory ranges from:";a[52]="A. Very low addresses up to 640KB";b[52]="B. Very high addresses down to 640KB";c[52]="C. The first 1KB of addresses starting at address zero";d[52]="D. All memory above the 1MB address";ans[52]="3";q[53]="DOS is designed to manage what memory range?";a[53]="A. Very low addresses up to 640KB";b[53]="B. Very high addresses down to 640KB";c[53]="C. The first 1KB of addresses starting at address zero";d[53]="D. All memory above the 1MB address";ans[53]="0";q[54]="The Interrupt Vector Table ranges from:";a[54]="A. Very low addresses up to 640KB";b[54]="B. Very high addresses down to 640KB";c[54]="C. The first 1KB of addresses starting at address zero";d[54]="D. All memory above the 1MB address";ans[54]="2";q[55]="What is the throughput of a 60ns 72-pin SIMM?";a[55]="A. 33.3MB/sec";b[55]="B. 66.6MB/sec";c[55]="C. 100MB/sec";d[55]="D. 133MB/sec";ans[55]="1";q[56]="What was the first CPU to feature protected mode?";a[56]="A. 80186";b[56]="B. 80286";c[56]="C. 80386DX";d[56]="D. 80386SL";ans[56]="1";q[57]="What was the first processor to be made from a form of CMOS?";a[57]="A. 8088";b[57]="B. 80286";c[57]="C. 80386";d[57]="D. 80486";ans[57]="2";q[58]="What was the first processor to be made specifically for laptops?";a[58]="A. 80286";b[58]="B. 80386DX";c[58]="C. 80386SL";d[58]="D. 80486SX";ans[58]="2";q[59]="What was the first processor to feature onboard cache memory?";a[59]="A. 80286";b[59]="B. 80386";c[59]="C. 80486";d[59]="D. Pentium";ans[59]="2";q[60]="Which statement is false concerning the difference between the 386DX and 386SX?";a[60]="A. The SX has no FPU";b[60]="B. The DX has a wider data bus";c[60]="C. The SX has a narrower address bus";d[60]="D. The SX has a similar pinout to the 80286";ans[60]="0";q[61]="How many stages does the 486 pipeline decoder have?";a[61]="A. 1";b[61]="B. 2";c[61]="C. 5";d[61]="D. unlimited";ans[61]="2";q[62]="An 80486 averages ____ clock cycles to complete the execution of an instruction?";a[62]="A. Between 1 and 2";b[62]="B. Between 2.25 and 4.5";c[62]="C. About 4.5";d[62]="D. About 12";ans[62]="0";q[63]="What memory technology is mostly associated with DIMMs?";a[63]="A. TTL DRAM";b[63]="B. EDO";c[63]="C. SDRAM";d[63]="D. DDR";ans[63]="2";q[64]="What is the maximum amount of RAM that the 80286 can address?";a[64]="A. 640KB";b[64]="B. 1MB";c[64]="C. 16MB";d[64]="D. 4GB";ans[64]="2";q[65]="Preemptive Multitasking depends on:";a[65]="A. Well written programs that pass control back to the OS kernel";b[65]="B. Well written kernel code that passes control back to the programs";c[65]="C. All active programs messaging each other and agreeing which can run";d[65]="D. Pulling control from the active program and giving it back to the kernel";ans[65]="3";q[66]="The cache MMU was moved onboard the processor to:";a[66]="A. Make protected mode possible";b[66]="B. Make multitasking possible";c[66]="C. To increase total addressable RAM";d[66]="D. To improve its speed and efficiency";ans[66]="3";q[67]="What was the first CPU with a 16-bit data bus?";a[67]="A. 8088";b[67]="B. 80286";c[67]="C. 80386";d[67]="D. 80486SX";ans[67]="1";q[68]="Normally the BIOS will initialize a video card into a VGA text mode whose memory base address is:";a[68]="A. A000:0000h";b[68]="B. F000:FFF0h";c[68]="C. B800:0000h";d[68]="D. F000:0000h";ans[68]="2";q[69]="The memory base address of the BIOS code in the EEPROM is:";a[69]="A. A000:0000h";b[69]="B. F000:FFF0h";c[69]="C. B800:0000h";d[69]="D. F000:0000h";ans[69]="3";q[70]="The memory CPU reset address is:";a[70]="A. A000:0000h";b[70]="B. F000:FFF0h";c[70]="C. B800:0000h";d[70]="D. F000:0000h";ans[70]="1";q[71]="The physical memory address that represents the 640KB boundary that separates conventional memory from the upper memory area is:";a[71]="A. A000:0000h";b[71]="B. F000:FFF0h";c[71]="C. B800:0000h";d[71]="D. F000:0000h";ans[71]="0";q[72]="The segment:offset notation, i.e. F000:FFF0h, is 16-bit numbers in what number system?";a[72]="A. Binary";b[72]="B. Binary Coded Decimal";c[72]="C. Octal";d[72]="D. Hexadecimal";ans[72]="3";q[73]="The notation &quot;F000:FFF0h&quot; for a program represents the contents of which registers?";a[73]="A. segment:offset";b[73]="B. code:data";c[73]="C. segment:index";d[73]="D. register:pointer";ans[73]="0";q[74]="The CPU calculates the physical address represented in segment:offset notation, i.e. F000:FFF0h by:";a[74]="A. Shifting the segment register 4 bits to the left then add them together";b[74]="B. Shifting the offset register 4 bits to the left then add them together";c[74]="C. Shifting the segment register 4 bits to the right then add them together";d[74]="D. Shifting the offset register 4 bits to the right then add them together";ans[74]="0";q[75]="The physical address represented by F000:FFF0h is:";a[75]="A. 1EFF0h";b[75]="B. 1FFFFh";c[75]="C. 1FFF0h";d[75]="D. FFFF0h";ans[75]="3";q[76]="The 8088 has twenty memory address bus lines &quot;A0-A19&quot;, what is the maximum number of discrete memory addresses that can be specified on this bus?";a[76]="A. 20";b[76]="B. 20 x 20 = 400";c[76]="C. 2^20 = 1,048,576";d[76]="D. 2^20 - 1 = 1,048,575";ans[76]="2";q[77]="On the twenty binary digit address bus, what the highest address?";a[77]="A. 20";b[77]="B. 20 x 20 = 400";c[77]="C. 2^20 = 1,048,576";d[77]="D. 2^20 - 1 = 1,048,575";ans[77]="3";q[78]="How can the CMOS be cleared by software?";a[78]="A. The system must be capable of booting from any drive to a DOS prompt";b[78]="B. The bootable and accessible disks must have a copy of DEBUG.EXE";c[78]="C. DEBUG must be run and the proper series of commands be issued";d[78]="D. All of the above";ans[78]="3";q[79]="The 80286 memory address bus is how wide and therefore supports how much RAM?";a[79]="A. 16-bit, 1MB";b[79]="B. 20-bit, 1MB";c[79]="C. 24-bit, 16MB";d[79]="D. 24-bit, 24MB";ans[79]="2";q[80]="When the 80286 resets it begins to emulate what CPU?";a[80]="A. 8088";b[80]="B. 8086";c[80]="C. 80186";d[80]="D. It does not emulate any other CPU";ans[80]="0";q[81]="When any CPU in the x86 family resets and emulates the 8088 this is referred to as:";a[81]="A. 8088 Emulation Mode";b[81]="B. Real Mode";c[81]="C. Protected Mode";d[81]="D. V86 Mode";ans[81]="1";q[82]="The 80286 was found to have a real mode bug in which it allowed the 21st bit of the segment:offset register calculation to activate that address bus line. What is this bus line called and what is the name of the area it makes available to DOS?";a[82]="A. A21, Upper Memory Area";b[82]="B. A20, Upper Memory Area";c[82]="C. A21, High Memory Area";d[82]="D. A20, High Memory Area";ans[82]="3";q[83]="What is the name of the driver invented to manage the HMA by adding a switching circuit for the A20 line to the keyboard controller?";a[83]="A. None, this support was added to the BIOS";b[83]="B. None, this support was added to IO.SYS";c[83]="C. CONFIG.SYS";d[83]="D. HIMEM.SYS";ans[83]="3";q[84]="Later what additional memory support function was added to HIMEM.SYS?";a[84]="A. Create and advertise Upper Memory Blocks for DOS to use";b[84]="B. XMS for making extended memory available to programs written to use it";c[84]="C. EMS for making expanded memory available to programs written to use it";d[84]="D. None of the above were added";ans[84]="3";q[85]="What is the maximum amount of RAM that the 80386 can address?";a[85]="A. 640KB";b[85]="B. 1MB";c[85]="C. 16MB";d[85]="D. 4GB";ans[85]="3";q[86]="Protected mode is basically:";a[86]="A. The CPU prevents devices from inteacting directly with each other";b[86]="B. The CPU prevents resource conflicts from happening";c[86]="C. The CPU prevents DOS and BIOS from interacting directly";d[86]="D. The CPU prevents programs from interacting directly";ans[86]="3";q[87]="Cooperative Multitasking depends on:";a[87]="A. Well written programs that pass control back to the OS kernel";b[87]="B. Well written kernel code that passes control back to the programs";c[87]="C. All active programs messaging each other and agreeing which can run";d[87]="D. Pulling control from the active program and giving it back to the kernel";ans[87]="0";q[88]="What was the number of blocks and sizes of the 486 L1 cache?";a[88]="A. 1 x 8KB";b[88]="B. 2 x 8KB";c[88]="C. 1 x 16KB";d[88]="D. 2 x 16KB";ans[88]="0";q[89]="Which multiplied 486DX has a misleading name?";a[89]="A. 486DX2/50";b[89]="B. 486DX2/66";c[89]="C. 486DX2/75";d[89]="D. 486DX4/100";ans[89]="3";q[90]="What was the first CPU to feature multiple pipelines and what are their names?";a[90]="A. 80486DX, master and slave";b[90]="B. Pentium, primary and secondary";c[90]="C. 80486DX, north and south";d[90]="D. Pentium, U and V";ans[90]="3";q[91]="What listed CPU feature determines the total amount of RAM the CPU can access? ";a[91]="A. Register width in bits";b[91]="B. Data bus width in bits";c[91]="C. Address bus width in bits";d[91]="D. Core speed in Megahertz";ans[91]="2";q[92]="What is the CPU feature that allows the chip to perform superscalar execution?";a[92]="A. SMM";b[92]="B. L1 Cache";c[92]="C. Register width";d[92]="D. Dual pipelines";ans[92]="3";q[93]="What is the CPU feature that enables BIOS APM to work?";a[93]="A. SMM";b[93]="B. L1 Cache";c[93]="C. Register width";d[93]="D. Dual pipelines";ans[93]="0";q[94]="What is the CPU feature that causes program code to be called 16 or 32 bit?";a[94]="A. SMM";b[94]="B. L1 Cache";c[94]="C. Register width";d[94]="D. Dual pipelines";ans[94]="2";q[95]="What is the CPU feature that greatly improves program execution speed?";a[95]="A. SMM";b[95]="B. L1 Cache";c[95]="C. Register width";d[95]="D. Dual pipelines";ans[95]="1";q[96]="What is the maximum amount of RAM that the 8088 can address?";a[96]="A. 640KB";b[96]="B. 1MB";c[96]="C. 16MB";d[96]="D. 4GB";ans[96]="1";q[97]="Which of the following is a 32-bit expansion bus?";a[97]="A. VESA";b[97]="B. MCA";c[97]="C. EISA";d[97]="D. All of the above";ans[97]="3";q[98]="Which of the following has the slowest clock?";a[98]="A. VESA";b[98]="B. MCA";c[98]="C. EISA";d[98]="D. PCI";ans[98]="2";q[99]="Which of the following can have the fastest clock?";a[99]="A. VESA";b[99]="B. MCA";c[99]="C. EISA";d[99]="D. PCI";ans[99]="0";